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<somlo>
shorne: got a notification from the kernel test robot (with you in the cc) re. the "move generic accessors to litex.h" -- any idea, is that a real problem or a glitch in the testing infrastructure ? :)
<geertu>
somlo: Is it bad? Was it CCed to a public list?
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<somlo>
geertu: forwarded it to you (yes mailing list in the cc, but I'd have to do "research" to find a public link :)
<somlo>
yeah, can't see how it's related to the patch it's actually complaining about :)
<somlo>
geertu: thanks for the msgid link-fu, I'll have to remember that! :)
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<geertu>
somlo: That .config seems to be completely broken. I get lots of
<geertu>
sh4-linux-gnu-objcopy: Unable to change endianness of input file(s)
<geertu>
sh4-linux-gnu-ld: cannot find certs/.tmp_gl_system_keyring.o: No such file or directory
<geertu>
=> ignore
<somlo>
yeah, tried to reproduce it yesterday, got a total incomprehensible mess, which leads me to suspect the kernel test robot is having a "moment" :)
<somlo>
but needed a sanity check to be sure...
<somlo>
thanks!
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<geertu>
somlo: The robot is right in that drivers/soc/litex/litex_soc_ctrl.o regressed due to your commit. But since everything else is broken, too, that doesn't matter.
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<somlo>
geertu: ok, for now I'll go with "return -EWORKSFORME", and assume that either nothing is wrong, or someone will send a bug report that at least one of us can comprehend :)
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<zyp>
acathla, dbus_cyc goes high when the cpu is trying to write, dbus_ack goes high when the write completes
<zyp>
looks like roughly two thirds of the time is spent just waiting for the write to go through
<acathla>
what could take so many cycles?
<zyp>
bus bridges, adapters, etc, I guess
<acathla>
Are there some wishbone signals I could watch?
<zyp>
cyc/stb on all the other wishbone segments involved
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<somlo>
acathla: it's not unusual for a cpu write to have to wait many (sometimes hundreds) of clock cycles for the valid/ready (or RTS/CTS) strobes to line up; I just never thought about LiteX in particular -- one would expect it's less of a problem here, since the cpu and memory clocks don
<somlo>
don't differ by so many orders of magnitude; but apparently it's still a thing
<somlo>
whether it's a real problem or just "the way things are", I am not qualified to say, but it shouldn't be super shocking, is all I'm saying :)
<acathla>
somlo, on a fomu/iCE40 @ 12MHz, I made some captures where it takes exactly 156 cycles between two writes
<somlo>
also depends on whether you're writing to a CSR, SRAM, or DRAM (the latter of which is likely involving LiteDRAM plus the actual memory, so it gets complicated)
<somlo>
acathla: just curious: is there a difference between a CSR (MMIO register) for a device, and SRAM (e.g. the stack used by the bios)?
<acathla>
somlo, I didn't check that.
<acathla>
I'm trying to write to a CSR UART
<acathla>
I'm shocked because I cannot fill a FIFO in parallel for an UART running at... roughtly 500KHz
<acathla>
I mean, it sends a byte every 1.8µs
<acathla>
Hum ,that's a measurement @20MHz, not 12, but that's almost the same
<zyp>
I think it's unreasonably slow FWIW
<zyp>
but there's obviously a reason it's that slow, so the question is what is blocking
<zyp>
acathla, can you try adding bus_interconnect also to the litescope capture?
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<zyp>
acathla, actually, looking closer at your trace, it seems to be taking 21 cycles, not 42
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<zyp>
I guess the issue here is that it's using a shared interconnect which is not very efficient, so it appears there's 8 ibus fetches, each consuming two cycles, making up 16 of the cycles, and those appear to be blocking the dbus
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<zyp>
once the ibus runs out of things to fetch, it releases cyc, allowing the interconnect to switch to serving the dbus, letting the write go through
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<zyp>
I might be totally mistaken, but if this works out to 21 cycles for one iteration of a 8 instruction write loop through an inefficient interconnect, it's fairly understandable
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