_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<shenki> shorne: did you make any progress booting linux?
<shenki> shorne: the soc has ram mapped to 0x4000_0000, so I don't see how loading it to 0 will work
<shenki> shorne: do we need to adjust the soc, or adjust the kernel?
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<shenki> we can adjust the soc by bulding '--cpu-variant linux', which changes the memory map to place RAM at 0x0
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<shorne> shenki: No luck yet, the tftp issue is fixed, then there was the mapping issue, but linux already maps too 0x0 with mor1k
<shorne> So I think we are mapped correctly,
<shorne> did you have any luck? I am using the mainline kernel, which at the end of last night I noticed has a differnt .dts setup compared to litex (i.e. uart is at a differnt address) but changing that didn't help either
<shorne> I am going to try the litex branch now
<shorne> That doesn't seem to work either, same issue, Liftoff then no response
<shorne> I will try again with litex-buildenv and mainline thats what I had been using before
<shorne> just to confirm I am sane
<shorne> OK, litex-buildenv with upstream kernel works just fine
<shorne> litex-boards with the litex-hub/linux/tree/litex-mor1kx branch doesn't seem to work
<shorne> I sent a mail to mateusz, hopefully he can explain which branches he is using then we can bisect
<somlo> shorne: would you mind trying https://github.com/litex-hub/linux/tree/litex-rebase ? I has the latest of everything I'm aware of (except vex/mor1k specific defconfigs)
<somlo> s/I has/It has/ :)
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<shorne> somlo: I did something else, I applied your 32-bit SOC patch to mainline and it works
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<somlo> shorne: nice, good to hear!
<somlo> also, thanks for the feedback on lkml -- I'll send out a v3 over the next day or two with all that stuff taken care of
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