11:05 <nickoe> hmm, maybe I am missing the clk definition to the flash

11:59 <nickoe> Ok, I think it is a bit more consistent now, at least the flash_erased command completed. I am not so sure about the mem_read though, https://dpaste.com/829M8MBP9

11:59 <tpb> Title: dpaste: 829M8MBP9 (at dpaste.com)

12:02 <nickoe> https://github.com/nickoe/litex-boards/commit/a9afce21025f2494ac9bd97f00a99535499c9d92

12:22 <nickoe> oh, so chaing dummy cycles from 9 to 8 in spi flash mode, it appeas to work, https://dpaste.com/CHSBJBAF3

12:22 <tpb> Title: dpaste: CHSBJBAF3 (at dpaste.com)

12:23 <nickoe> I also see my flash chip listed in https://github.com/litex-hub/litespi/blob/55926a6c035da37123fa467779a6b72cdd26d061/litespi/modules/generated_modules.py#L7256-L7275, maybe I should swith to using the litespi module instead?

12:23 <nickoe> _florent_: What do you think?

12:23 <nickoe> Does it support QSPI mode as well?

12:30 <nickoe> _florent_: mmm, how does one go about flashing the flash now? https://github.com/enjoy-digital/litex/commit/41964f945cee71337e8e0998d597086b2ef94f77

12:33 <nickoe> Can I flash it via JTAG somehow?

12:55 <nickoe> Reading XAPP586 it appears that ISE/IMPACT flashes a custom bitstream to the FPGA to route through the SPI mode from the JTAG to sprogram it?

13:19 <nickoe> Does the netv2 support it? https://github.com/enjoy-digital/netv2/blob/14905f90ffdefadc396f2a1df8675d59ee151516/netv2.py#L227-L229

14:46 <nickoe> Why does litex_term.py ned a serial port if using it over jtag?

14:48 <nickoe> hmm, ok, it seems to work with that AND the UART then

14:48 <nickoe> great!

14:49 <nickoe> https://i.snipboard.io/cojGJh.jpg

14:50 <nickoe> I added the snippet in https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC#create-scripts-to-communicate-from-the-host-pc-with-the-bridge in that test_identifier.py script. But I wonder why it does not list all my registers.

14:53 <nickoe> ah, ok, an outdated csr.csv that I had laying around

15:15 <nickoe> This wishbone remote client stuff if pretty cool. I am not sure how it works, but it apperas thta if I just do writes to a regiter in a forloop that I can run that with about 20Hz. It apperas as if the operations are buffered or offloaded to the server, as the test script has returned, but the registeres are still updated. That I can see with the logic analyzer on some pins.

15:15 <nickoe> _florent_: I know this interface is not intended to be a streaming interface, but is it possible to make considerably faster?

18:16 <nickoe> mmm ERROR: [DRC MDRV-1] Multiple Driver Nets: Net OBUFDS_1/OB has multiple drivers: OBUFDS_1/N/O, and OBUFDS_1/P/O.

18:23 <nickoe> vivado does not seem that happy with my attempt to make a differential clock output, https://dpaste.com/42VXRZDUS

18:23 <tpb> Title: dpaste: 42VXRZDUS (at dpaste.com)

18:34 <nickoe> Ok, that was becasue I had the same signal to both outputs the the DifferentialOutput special.. but now.. ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'

18:55 <_florent_> nickoe: sorry I'm no very present the weekend here, but it seems you are solving the issues yourself :) (and so also learning the hard way)

18:55 <nickoe> yeah, sort of ,but now I am utterly stuck

18:56 <nickoe> I am trying to put a clock signal out as a differential output

18:57 <nickoe> _florent_: I did this https://github.com/nickoe/litex-boards/commit/ce960e74096d36261f22bddac46ed54c4ee5c6c8

18:59 <nickoe> log for the latest from vivado https://dpaste.com/7QSY5TF55

18:59 <tpb> Title: dpaste: 7QSY5TF55 (at dpaste.com)

19:01 <nickoe> mmm CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, the positive port (P-side) 'dac_clkx_p' of a differential pair cannot be placed on a negative package pin 'L4' (IOBS). [/home/nickoe/litex_test/dangerous_litex/litex-boards/litex_boards/targets/build/mars_ax3/gateware/mars_ax3.xdc:409]

19:02 <nickoe> Ok, made some minor fixes... crossed fingers!

19:08 <nickoe> _florent_: Is there not compatible IOStandard I can use for this? ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:

19:08 <nickoe> dac_clkx_p (DIFF_HSTL_II_18, requiring VCCO=1.800) and dac_data_a[0] (LVCMOS33, requiring VCCO=3.300)

19:08 <nickoe> I tried to add DIFF_LVCMOS33, but

19:08 <nickoe> CRITICAL WARNING: [Common 17-69] Command failed: Invalid I/O Standard 'DIFF_LVCMOS33'. Default I/O Standard is used instead [/home/nickoe/litex_test/dangerous_litex/litex-boards/litex_boards/targets/build/mars_ax3/gateware/mars_ax3.xdc:410]

19:13 <nickoe> My DAC, MAX5854 "The differential input accepts an input range of ≥0.5V P-P and a common-mode range of 1V to (CV DD - 0.5V), making the part ideal for low-input amplitude clock drives."

19:13 <nickoe> But unfortunately the clock signal and the data signals are in the same bank.

19:22 <nickoe> https://i.snipboard.io/lLpmHI.jpg

19:25 <nickoe> I guess I can run them as regular outputs then, somehow

20:27 <nickoe> mmm, I don't quite get an output.. shouldn't I be able to do

20:27 <nickoe> self.comb += dac_plat.clkx_n.eq(self.crg.cd_sys.clk)