06:59 <_florent_> nickoe: LiteDRAMDMAReader has two endpoints: a sink to provide your read request and a source that will return the data

07:00 <_florent_> so you can just set sink.valid.eq(1), sink.address.eq(the_address_you_want_to_read)

07:00 <_florent_> then wait sink.ready to be 1

07:00 <_florent_> and data will be returned on source.data when source.valid is 1

09:32 <_florent_> cr1901_modern: just for info, the standard Microwatt variant (without irq) is fixed by https://github.com/enjoy-digital/litex/commit/a51bf60712bac51077d849e037f060fb02f59614

09:32 <_florent_> you can simulate it with: lxsim --cpu-type=microwatt --cpu-variant=standard+ghdl

09:33 <_florent_> I'm now going to see if I can build the OrangeCrab target

09:46 <_florent_> cr1901_modern: I just tested this: ./orangecrab.py --cpu-type=microwatt --cpu-variant=standard+ghdl --integrated-rom-size=0xa000 --build

09:46 <_florent_> Autoname pass is ok, but this is using too much resources:

09:47 <_florent_> https://www.irccloud.com/pastebin/8VFsgsVD/

09:47 <tpb> Title: Snippet | IRCCloud (at www.irccloud.com)

09:47 <_florent_> so I would recommend testing on a larger FPGA first

09:53 <cr1901_modern> _florent_: Okay, thanks for testing. Could you give me your commit hash for litex as well as _any_ diffs you applied to pythondata-cpu-microwatt?

09:54 <cr1901_modern> Also, I'm afraid I don't have any FOSS FPGA that's bigger LOL. Noted that microwatt is rather large

09:55 <cr1901_modern> _florent_: Oh wait... I tested --cpu-variant=standard+ghdl+irq

09:55 <cr1901_modern> That's was the variant that was failing an assert

09:55 <_florent_> cr1901_modern: yes, I also have the assertion failure with it, I'm currently looking at this

09:56 <cr1901_modern> Awesome, tyvm

09:56 <cr1901_modern> I'm going to pull and test your command line immediately

09:58 <cr1901_modern> My changes: http://ix.io/2QkG

09:58 <_florent_> https://github.com/enjoy-digital/litex/commit/91cebb51598c32ef616ef70bd63251658181fb3b fixes the irq variants.

09:58 <cr1901_modern> Awesome

09:59 <cr1901_modern> Just to reiterate, new versions of binutils error out on command line args it doesn't understand

09:59 <_florent_> here the diff I have in pythondata_cpu_microwatt:

09:59 <cr1901_modern> -nodefaultlibs is one of these options

09:59 <_florent_> https://www.irccloud.com/pastebin/vCJzKB8d/

09:59 <tpb> Title: Snippet | IRCCloud (at www.irccloud.com)

09:59 <cr1901_modern> tyvm for the diff

10:00 <cr1901_modern> Idk what you want to do about the binutils problem- it may not affect you rn. But it's a heads-up

10:01 <_florent_> cr1901_modern: would you mind opening an issue for this? We could also discuss this other developers familiar with Microwatt

10:01 <cr1901_modern> Which part? The autoname problem or the binutils problem?

10:02 <cr1901_modern> (I can do both of course)

10:02 <_florent_> the autoname problem seems more related to others tools (GHDL-Synth/Yosys?)

10:03 <_florent_> but for binutils we can probably do something in LiteX

10:11 <cr1901_modern> _florent_: https://github.com/enjoy-digital/litex/issues/825

10:15 <cr1901_modern> >Info: DP16KD: 56/ 56 100%

10:15 <cr1901_modern> That's not good... ._.

10:52 <_florent_> cr1901_modern: moving the BIOS to SPI Flash (as done on Fomu/Icebreaker) could help for this.

11:00 <cr1901_modern> Sure... but I'm still surprised

11:14 <nickoe> _florent_: Can I run a simulation of my entire soc? I see yhe antmicro blog about it using renode for the cpu emulation amd verlator for som modules, but I am not sure how to set this up properly. Can I use lxsim entirely?

13:16 <_florent_> nickoe: litex_sim is indeed a simulaton of a LiteX SoC. The default is something basic (CPU + ROM + SRAM + UART), but you can also enable Ethernet/SDRAM

13:17 <_florent_> we are using this to boot linux in simulation for example in https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/sim.py

14:28 <nickoe> _florent_: I don't need linux, just bare metal fw

15:52 <shoragan> _florent_, how would BIOS from SPI flash work? does that SPI controller have mmap support?

20:26 <nickoe> shoragan: It just works.. :D I think it is mmapped

20:26 <nickoe> or can

20:26 <nickoe> or maybe I misunderstood you

20:26 <nickoe> mmm

20:27 <shoragan> nickoe, thanks, then i found the right part in the soc integration :)

20:30 <nickoe> :)

21:34 <nickoe> _florent_: How do I specify the simulation to run my target?

22:04 <nickoe> _florent_: by the way, I did successfully make the linux-on-litex-vescrisv boot the simulation. It appears to run on one core only (on the host) is that expected?

23:24 <nickoe> mm, trying to follow the example and make a sim.py, but it keeps complaining that for example: TypeError: litex.soc.integration.soc_core.SoCCore.__init__() got multiple values for keyword argument 'with_uart'

23:24 <nickoe> I can't see where it comes from in the first place

23:25 <nickoe> https://github.com/nickoe/litex-boards/commit/065b2272fd4d723ff6f1c85c64c92ee2e168ebac

23:28 <nickoe> When I get to https://github.com/nickoe/litex-boards/commit/065b2272fd4d723ff6f1c85c64c92ee2e168ebac#diff-d425e98545324591d65661ee2e287a013bc2633e6dfdb211f9ac66551c2a619aR351 it appears that soc_sdram_args(parser) seems to break it..

23:34 <nickoe> https://dpaste.com/4MXHGXYLU mmm

23:34 <tpb> Title: dpaste: 4MXHGXYLU (at dpaste.com)

23:36 <nickoe> I guess I should just admit I am stuck for today and go to bed.

23:40 <nickoe> which riscv64-unknown-elf-ld

23:40 <nickoe> /usr/bin/riscv64-unknown-elf-ld FWIW