#litex on 2021-03-22 — irc logs at freenode.irclog.whitequark.org

2020-02-07 11:13 _florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex

00:00 tpb has quit [Remote host closed the connection]

00:00 tpb has joined #litex

00:08 lkcl has quit [Ping timeout: 264 seconds]

00:09 HoloIRCUser2 has joined #litex

00:12 HoloIRCUser has quit [Ping timeout: 240 seconds]

00:21 lkcl has joined #litex

00:40 lf has quit [Ping timeout: 244 seconds]

00:40 lf has joined #litex

01:12 lkcl has quit [Ping timeout: 264 seconds]

01:26 lkcl has joined #litex

02:37 Degi_ has joined #litex

02:38 Degi_ is now known as Degi

02:38 Degi has quit [Ping timeout: 240 seconds]

03:53 futarisIRCcloud has joined #litex

04:12 lkcl has quit [Ping timeout: 240 seconds]

04:26 lkcl has joined #litex

04:52 Bertl_oO is now known as Bertl_zZ

04:58 lkcl has quit [Ping timeout: 240 seconds]

05:11 lkcl has joined #litex

05:38 lkcl has quit [Ping timeout: 256 seconds]

05:51 lkcl has joined #litex

05:59 futarisIRCcloud has quit [Quit: Connection closed for inactivity]

06:51 rozpruwacz has joined #litex

07:03 scientes_ has quit [Ping timeout: 240 seconds]

07:53 RaivisR_ has joined #litex

07:53 HoloIRCUser2 has quit [Read error: Connection reset by peer]

07:53 HoloIRCUser1 has joined #litex

07:56 RaivisR has quit [Ping timeout: 256 seconds]

08:06 lkcl has quit [Ping timeout: 240 seconds]

08:16 HoloIRCUser1 has quit [Ping timeout: 272 seconds]

08:19 lkcl has joined #litex

08:26 FFY00_ has quit [Ping timeout: 244 seconds]

08:27 FFY00_ has joined #litex

08:55 lkcl has quit [Ping timeout: 260 seconds]

09:09 lkcl has joined #litex

09:57 _whitelogger_ has quit [Remote host closed the connection]

09:59 _whitelogger_ has joined #litex

10:11 rozpruwacz has quit [Ping timeout: 245 seconds]

10:12 rozpruwacz has joined #litex

10:47 st-gourichon-fid has quit [Quit: ZNC - https://znc.in]

10:47 st-gourichon-fid has joined #litex

11:28 Bertl_zZ is now known as Bertl

11:41 Melkhior has quit [Quit: Connection closed]

13:40 <keesj> is there an example of include some verilog code, perffably I would like a wishbone slave where I can instanciate my module

13:41 <keesj> I did find litex_read_verilog (to read convert to python) but from memory there was also some "include" possibilites

13:50 <acathla> keesj, find an example with something like : "platform.add_source()"

14:11 <_florent_> keesj: you have a look at: https://github.com/enjoy-digital/litex/wiki/Reuse-A-Verilog-VHDL-nMigen-Core

14:12 <_florent_> and also to some cores integrated in Betrusted, I2C for example: https://github.com/betrusted-io/gateware/blob/master/gateware/i2c/core.py

14:26 Bertl is now known as Bertl_oO

14:29 <keesj> ok nice.. and.. if I want to replace my Soc with magic python code I set cpu_type to None?

14:30 <keesj> I remember also somebody being able to use the uart and debug on fomu

14:31 <_florent_> setting cpu_type=None removes the CPU from the SoC (ie you just get the SoC infrastructure)

14:32 <keesj> becase the litescope adds with_etherbone but I guess there must then be a similar options for taking over the serial as wishbone master

14:33 <_florent_> yes with add_uartbone

15:00 <keesj> yes, it looks like serial is still already obtained by SoCCSRHandler https://pastebin.com/1PeBgNnn even when I set the cpu type to None

15:00 <tpb> Title: INFO:SoC: __ _ __ _ __ INFO:SoC: / / (_) /____ | |/_/ - Pastebin.com (at pastebin.com)

15:12 <acathla> keesj, you must set : kwargs["uart_name"] = "crossover"

15:13 <acathla> so your uart won't be connected to anything but accessible through wishbone reads/writes

15:13 <keesj> that does produce a different result :P

15:13 <acathla> and the real uart used as a wishbonebridge

15:15 <keesj> https://pastebin.com/pV5yJZjL a lot of grep and code reading involved here :P

15:15 <tpb> Title: INFO:SoCBusHandler:csr added as Bus Slave.INFO:SoCCSRHandler:bridge added as C - Pastebin.com (at pastebin.com)

15:17 <keesj> getting hot !

15:21 <keesj> yup.. awesome...

15:37 <keesj> now I need to combine this with a verilog module, nice

15:57 rozpruwacz has quit [Ping timeout: 260 seconds]

16:00 david-sawatzke[m has quit [Quit: Idle for 30+ days]

17:00 Bertl_oO is now known as Bertl

17:33 pftbest_ has joined #litex

17:36 pftbest has quit [Ping timeout: 240 seconds]

17:57 kgugala has quit [Ping timeout: 264 seconds]

17:57 kgugala has joined #litex

18:05 kgugala has quit [Read error: Connection reset by peer]

18:05 kgugala has joined #litex

18:08 kgugala_ has joined #litex

18:09 kgugala has quit [Read error: No route to host]

18:09 kgugala has joined #litex

18:12 kgugala_ has quit [Ping timeout: 245 seconds]

18:19 kgugala_ has joined #litex

18:21 kgugala has quit [Ping timeout: 265 seconds]

18:22 kgugala has joined #litex

18:24 kgugala_ has quit [Read error: Connection reset by peer]

18:24 kgugala__ has joined #litex

18:27 kgugala has quit [Ping timeout: 240 seconds]

18:37 kgugala has joined #litex

18:41 RaivisR_ has quit [Quit: Leaving]

18:41 kgugala__ has quit [Ping timeout: 256 seconds]

19:05 shoragan has quit [Ping timeout: 258 seconds]

19:08 shoragan has joined #litex

23:11 kgugala has quit [Ping timeout: 256 seconds]