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<sajattack[m]>
has anyone flashed the cle-215 with a jlink that could give me a hand?
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<sajattack[m]>
I think my openocd version and my jlink fw version are out of sync
<sajattack[m]>
but both are latest :/
<zyp>
I'd suspect you got the pinout wrong
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<sajattack[m]>
I don't think so, in my hatebin link it's communicating enough to read a device id, but openocd is giving a libusb error when I try to flash
<sajattack[m]>
despite running as root and everything
<zyp>
looks to me like it's trying to read the device id and just getting garbage back
<sajattack[m]>
maybe
<zyp>
which I guess is how it'd look if you swapped JTMS and JTDI
<RaivisR__>
also, 25MHz and breadboard?
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<zyp>
says reduced to 4 MHz
<zyp>
but yeah, might be worth reducing that too
<RaivisR>
ah, yes, let me introduce myself, got ecp5 vip, trying to put litex on it
<RaivisR>
or rather did it yesterday already, today adding dram, peripherals and putting linux on it
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<sajattack[m]>
wiring looks right to me, lowered the clock, same behaviour
<sajattack[m]>
even tried swapping tdi and tms
<sajattack[m]>
whoa it found a xilinx device id
<sajattack[m]>
magic
<sajattack[m]>
grounds were fucked
<sajattack[m]>
still having libusb errors but led turned solid
<sajattack[m]>
but I guess I need a uart cable to check further?
<RaivisR>
to see litex bootloader prompt? i am n00b at this but yes, i had only clock, reset and serial in platform definition and it showed me boobloader prompt
<sajattack[m]>
this is the part that seems like bad jlink firmware
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<zyp>
sajattack[m], you can use the crossover uart over pcie
<zyp>
but first you'll want to make sure the new gateware enumerated over pcie
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<sajattack[m]>
Ah yes, lspci, should have thought of that
<keesj>
Hi, I back... :P I want to do a small project with tinyfpga_bx and a soft core.
<keesj>
it looks like this should be almost trivial at there is already a board file and I just copyed the .py file and would like to get to hello world
<keesj>
even nicer if this can be combined with and USB serial .. but that probably won't fit
<keesj>
so in the link I posted above the code is compiled to xip and only the minimal sram is used. this setup is different from the commited code
<zyp>
you might want to look at how the fomu does usb with litex
<keesj>
thanks for the tip
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<keesj>
I was messing around with the firmware section but I think the ROM/BIOS it not functioning
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<RaivisR_>
aparently just throwing all the pins at litedram does not quite work, oh well, more digging
<rozpruwacz>
_florent_: did You get my message i'v sent yesterday around 3pm utc ? I disconnected from the irc and may lost your reply.
<RaivisR_>
single chip works, now to figure how to make them both work
<keesj>
I am looking at nand flash (single data rate) and would like to read out some data from it. When i look at the timing diagrams (the data in no clocked) there is a varatity of different setup and hold times e.g. https://i.imgur.com/3FgJSvH.png is there a nice way to handle this "complex" set of changes ? I am currently doing a clock divider and a state machine
<RaivisR_>
i stand corrected - worked on first boot
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<keesj>
I did have a look a glawgow code that is supposed to understand parallel nand but I don't have the board
<keesj>
RaivisR_: nice
<RaivisR_>
well, not quite my definition of nice, but yes, at least something works for some time :)
<keesj>
sometimes.... I am quite happy when something just works (for some time0
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<_florent_>
rozpruwacz: sorry, I got the message yes but haven't been able to look at it yet
<_florent_>
RaivisR_: which board are you testing?
<_florent_>
RaivisR_: can you share the BIOS log if failing?
<RaivisR_>
i am learning, on ecp5 vip, it is more of me being total noob than anything else
<RaivisR_>
i am rolling my own platform file as I go
<_florent_>
ok, for the initial tests, I would recommend using the same sys_clk_freq than the Versa ECP5
<RaivisR_>
versa has single sdram chip, this one has two
<_florent_>
What's the behaviour when you say "something works for some time"?
<rozpruwacz>
_florent_: sure, no problem :)
<RaivisR_>
if I define pins for only one chip, initial memory test passes, on consecutive runs it fails, but I am sure it is me doing something wrong, i am just talking to myself loud (silently hoping that maybe someone will yell - i know that one!) :)
<_florent_>
RaivisR_: OK, testing only one chip initially is a good idea, you could switch to the two chips when stable with one :)
<RaivisR_>
I´ll go all in :) digging through sources and trying understand what is what and why helps to soak in the feel original dev had when writing the whole thing
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<RaivisR>
making progress, bus and addr errors both 0, data errors a lot
<RaivisR>
if I have 4GiB address space and 2GiB sdram, I probably should think about where do I put it
<somlo>
_florent_: is there an easy way to capture a module's FSM state as one of the entries in `analyzer_signals` ?