_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<sajattack[m]> yeah it's definitely a problem on newer kernels
<sajattack[m]> I spun up an ubuntu 18.04 vm with pcie passthrough and it works now
<sajattack[m]> 9Gbps DMA
<sajattack[m]> happy to look into a fix if I have time and you point me in the right direction
<sajattack[m]> got a lot of this while messing about with litex_server
<sajattack[m]> lots of etherbone timeouts too but I think I might have resolved that one
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<Akshar> Hey! All. I am total new here.
<hansfbaier> Akshar: Hi
<Akshar> I want to build one SBC which has litex core and most of the things that rasberry pi kind of kit includes.
<Akshar> But under 80$
<Akshar> is it feasible?
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<hansfbaier> Ak
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<keesj> sajattack[m]: what am I looking at. is your fpga on the pcie of your host pc?
<sajattack[m]> yes
<keesj> 1048576 == 0x100000
<sajattack[m]> yeah pretty small
<keesj> cool
<sajattack[m]> so I don't know where it's set and why it's too small
<keesj> welll for mmap you can probably trace the calls (e.g. use strace) but . .my guess would be that the problem is in addr
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<keesj> the address is over 4g over the start
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<_florent_> sajattack[m]: To limit BAR0 size, the CSR are remapped internally to address 0, so with LiteX Server over PCIe you have to use this for now: https://github.com/enjoy-digital/litex/commit/58701cc48cd1778cec14196d86ab4d75d7c28624
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<mithro> zyp: Were was the USB stuff you were doing again?
<mithro> zyp: Do you twitter?
<zyp> no
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