_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<shorne> interesting, I have been having issues with litex bios booting linux off sdcard, when I turn on sdcard_debug it boots, when I turn if off it doesnt boot
<shorne> it looks like some kind of timing issue
<shorne> with some debug it shows the f_mount call fails
<shorne> looking more
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<shorne> Is there a fast way to flash a new bios to the board? If I make c changes and do " ./arty.py ..platform options.. --load " it doesn't update the bios
<shorne> I seem to have to do "./arty.py ...option... --build; ./arty.py ...options... --load" which requires waiting for the bitstream to build
<shorne> the --no-compile-gateware option doesn't seem to do anything
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<zyp> the bios is stored in blockram initialization in the bitstream so updating it requires either rebuilding the bitstream or rewriting the bitstream to change blockram contents, and I don't think the latter is supported
<shorne> zyp: thats what I figured, but wasn't sure, thanks for clarifying
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<_florent_> shorne: That's not supported directly in the LiteX-Targets, but it's possible to easily rebuild the BIOS and reload it
<_florent_> With a bridge in your SoC (for example JTAGBone in your case), you can set integrated_rom_mode to "rw": https://github.com/enjoy-digital/litedram/blob/master/bench/arty.py#L76
<_florent_> and then use a simple script to reload the ROM and reset the SoC: https://github.com/enjoy-digital/litedram/blob/master/bench/common.py#L95-L109
<_florent_> in case reseting the full SoC breaks the bridge, you could comment this: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L939-L944
<_florent_> this will only reset the CPU and not the whole SoC
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<_florent_> nats`: Thanks for the minimal repro, this was an issue in LiteX, the default CRG is probably not used that often: https://github.com/enjoy-digital/litex/commit/e48b269d77567e251d34bd501d8cb390a91ee675
<_florent_> nats`: I'm planning to cleanup/improve litex.build in not too long...
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<shorne> _florent_: thanks, I will try that tomorrow
<shorne> the sdcard failing to boot seems mostly due to something wrong with how I built my sdcard partition table/fat32 filesystem
<shorne> I am not sure why enabling sdcard_debug statements fixes the issue, but I am trying to get to the root cause
<gatecat> anyone seen "TypeError: Expression of unrecognized type: 'ClockSignal'" before?
<gatecat> it seems to be related to using `wishbone.SRAM` to read from a memory
<gatecat> ah, my error, wishbone.SRAM isn't supposed to be a submodule
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<somlo> shorne: with libfatfs all FAT partition sizes *should* work, but empirically I've had better luck with fat16
<somlo> * in LiteX bios (i.e., for booting from the sdcard)
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<nats`> _florent_, you mean that using the default clock isn't mapped correctly ?
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<_florent_> nats`: There was a typo in the code preventing the constraint to be generated.
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<shorne> _florent_: it does seem to work, after the rom load and reset I need to wait about 30 seconds (maybe jtag transfer?)
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<zyp> in case anyone is interested; I started building a wrapper around luna: https://paste.jvnv.net/view/ODFvB
<tpb> Title: JVnV Pastebin View paste – Untitled (at paste.jvnv.net)
<zyp> just had my first luna-in-litex USBDevice enumerate :) haven't tested the streams yet
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