<_florent_>
leons: Initial boards support are generally not perfect/complete, so integrating your board even with DRAM not yet working would be perfectly fine (we would just avoid enabling DRAM or list the limitation). This is also a good way to work together on this or get help from other developers having the same board.
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<Melkhior>
Hello,
<Melkhior>
Got myself a new board with an on-board Ethernet for Litex, but when configuring an IP under Linux I only get:
<Melkhior>
liteeth f0004800.mac eth0: LITEETH_READER_READY timed out
<Melkhior>
repeated a few times.
<Melkhior>
Only trace I found of the error message is a year-old discussion...
<Melkhior>
Any idea ?
<Melkhior>
Board is a Qmtech Wukong (cheap Artix 7 100k, comfortably fit 4 VExRiscv cores with all the bells and whistles :-) )
<Melkhior>
Running the "default" kernel for linux-on-litex-vexriscv:
<mikeK_de1soc>
Hi Florent! I got the Video terminal to work on the DE1-SoC! How do I use the keyboard now? Or can I log in with the lxterm? I am not sure how to do this.. Thanks. MikeK
<Melkhior>
Also reconfigured the IP in the BIOS, but the interface doesn't ping and the server doesn't see any request when trying to netboot...
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<Melkhior>
OK, so I fixed the platform/targets definition of the board (the hardwxare description says it's a GMII interface), now Linux doesn't complaint anymore ; the interface sends ARP request, but doesn't seen the answer and doesn't ping, guessing it never receives data...
<Melkhior>
I have a 80 MHz system clock, maybe it's too slow for GbE ?
<_florent_>
mikeK_de1soc: Yes the Video Terminal is a recopy of the UART output, so you still can interact with the SoC with lxterm
<_florent_>
Melkhior: The best would be to get netboot behaving correctly first yes
<_florent_>
You can enable software debug traces in the BIOS with software_debug=True:
<_florent_>
You can also try to play with MDIO from the BIOS to dump/modify the PHY registers
<Melkhior>
_florent_ not sure I understand... I don't even understand where the clocks for the ethernet comes from; there's a 125 MHz RX from the board, but I have no 125 MHz clock in my design to supply the GTX clock...
<Melkhior>
so can I still run GbE ? But then for MII mode (fast ethernet I guess) I need a 25 MHz clock, I don't have that either
<Melkhior>
so I'm a bit lost long before the delay stuff :-/
<Melkhior>
litex> mdio_dump 0 16
<Melkhior>
MDIO dump @0x0:
<Melkhior>
0x00 0x1140
<Melkhior>
0x01 0x7969
<Melkhior>
0x02 0x001c
<Melkhior>
0x03 0xc915
<Melkhior>
0x04 0x05e1
<Melkhior>
0x05 0xc5e1
<Melkhior>
0x06 0x000f
<Melkhior>
0x07 0x2001
<Melkhior>
0x08 0x6001
<Melkhior>
0x09 0x0200
<Melkhior>
0x0a 0x3c00
<Melkhior>
0x0b 0x0000
<Melkhior>
0x0c 0x0000
<Melkhior>
0x0d 0x0000
<Melkhior>
0x0e 0x0000
<Melkhior>
0x0f 0x3000
<Melkhior>
are those the CSR from "class LiteEthPHYMDIO" ?
<_florent_>
The TX clock will be generated from the RX clock
<Melkhior>
So if my cd_idelay is defined as 2*sys_clk_freq it's not 200 MHz and it migh mess things up ? The board does that (so does mine), probably because the MMCM sometimes fails to generate all the clocks if they are unrelated in requency...
<_florent_>
You can see here that the delay can be adjusted: In the FPGA, through the Clk traces and also in the PHY
<_florent_>
yes you have to make sure that the S7IDELAYCTRL reference clock is 200MHz
<_florent_>
if you have difficulties generating all the clock with a single PLL, you can also use a specific PLL for the cd_idelay
<Melkhior>
Yes, I think I get that, I had to try to understand the principle to get the set_input_delay/set_output_delay right to interface with the SBus (all 82 parallel signals of it)
<Melkhior>
OK, I can use more than one PLL ? good news
<Melkhior>
rebuilding with the proper idelay clk & the software debug
<Melkhior>
I will not find the trace information for this board, el-cheapo board from aliexpress
<Melkhior>
(but if everything works out-of-the-box I don't get to learn)
<Melkhior>
thanks for the pointers I'll try to make sense of things
<_florent_>
yes you can use multiple PLLs (on a xc7a100t you have 6 CMTs (1 MMCM + 1 PLL))
<Melkhior>
also, on this board, the micro-sd card (on a pmod thingy) works fine, and I was able to write a file from Linux ... my own board must have an issue :-(
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<Melkhior>
OK, if I get the ethernet working I'll do a PR for it
<Melkhior>
thanks again
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<Melkhior>
_florent_ update: with the fixed idelay clock, the system netboot just fine, but linux still won't ping or be pinged or do any tcp traffic. As far as I can tell, it does emit the ARP request but doesn't see the reply (the arp table is always 'incomplete' for all other systems)
<Melkhior>
anyway it's already progress :-)
<leons>
Melkhior: I had that exact same issue yesterday!
<leons>
Though after reading florent's statements, my solution is probably wrong and it's still flaky for me
<leons>
I just tried adding `self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/125e6)` (so adding the constraint for both RX and TX clocks)
<leons>
It works with my Desktop NIC, but my Ethernet switch doesn't like it. I suppose this is not accounting for the phase offset required
<leons>
Disclaimer: I don't understand much of this, just trial and error on my side :)
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