m4ssi has quit [Remote host closed the connection]
<thorns514>
if I have a uart that I want to use to serialboot some firmware, and then reuse in lxserver to connect to litescope_cli, is this possible ?
apolkosnik[m] has quit [Ping timeout: 252 seconds]
shoragan[m] has quit [Ping timeout: 245 seconds]
sajattack[m] has quit [Ping timeout: 248 seconds]
ric96 has joined #litex
promach3 has joined #litex
CarlFK has joined #litex
sajattack[m] has joined #litex
leons has joined #litex
shoragan[m] has joined #litex
disasm[m] has joined #litex
xobs has joined #litex
JJJollyjim has joined #litex
jryans has joined #litex
apolkosnik[m] has joined #litex
Bertl is now known as Bertl_zZ
Melkhior has joined #litex
kgugala_ has joined #litex
kgugala has quit [Ping timeout: 240 seconds]
thorns514 has joined #litex
_whitelogger has joined #litex
kgugala_ has quit [Read error: Connection reset by peer]
kgugala has joined #litex
Bertl_zZ is now known as Bertl
<thorns514>
if I have a USB debug bridge working with a valenty DummyUsb core in my soc, verified with wishbone-tool, should I expect this also to work with litescope using lxserver?
<zyp>
yes
<dkozel>
Is there a way to load a new bitstream to the CLE-215 over LitePCIe _florent_ ?
<zyp>
isn't that what the ICAP module is for?
<thorns514>
ok thanks, I need to figure out why it reports no regs then ..
<dkozel>
zyp: I'll go take a look
<dkozel>
First glance is that should allow partial reconfiguration which is essentially the goal. Most literature is about reconfiguring from an internal softcore, but presuably the interface can be wired to an external facing bus like PCIe
<zyp>
IIRC the litex module just exposes it as a couple of registers on the CSR bus
m4ssi has joined #litex
<_florent_>
dkozel: with the Acorn, adding S7SPIFlash as a flash submodule will allow you to update the bistream in SPI Flash with the LitePCIe utilities
<zyp>
_florent_, question: what does generic_platform.Inverted do?
<thorns514>
does the litescope cli/RemoteClient need the soc csr.csv (with all the CSR regs and memory map etc), in addition to the analyzer CSV with the tapped wires? it's complaining that the remote has no "regs", and it works if I rename the file that I saved my soc --csr-csv to as csr.csv (which the RemoteClient seems to default to) ...
<zyp>
the reason I'm asking is because I'm about to put some more work into my luna wrapper, and I want it to automatically adapt to the phy used on the platform
<zyp>
ulpi phys can have reset being either active high or active low, and the clock can either be an input or an output
<zyp>
for the clock I'm planning to distinguish on whether the pads have a clk or clk_o signal, and I'm wondering if I should do similar with reset, or if this is what the Inverted annotation is meant for
<_florent_>
zyp: Inverted was introduced as a quick workaround for some NeTV2 use cases, I'm not sure we should expand it for now (at least I would like to revisit it first)
<zyp>
I see, that explains why I didn't see much use of it when I grepped around
<_florent_>
thorns514: LiteScope indeed also needs the csr.csv to get the register mapping (analyzer.csv only provides the mapping of the analyzer signals)
<zyp>
in that case I think I'll call it rst_n if it's active low
<thorns514>
_florent_: thanks, yeah I am prepping a PR to add a better warning if your CSR is not csr.csv. But I'm still trying to get a good trace first. I'm triggering on the CYC of my bus slave for instance, but the trace that pops out (immediately) has no CYC raise in it