_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<_florent_> thanks tcal for filling the issue, I have other issues to look at first but will try to think about it while also trying to expose VexRiscv-SMP's parameters to targets
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