_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<nickoe> _florent_: What could the reasons be that LiteDRAMDMAReader() will appear to buffer stuff in the fifo, but it does not seem like the data is anything but zeros?
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<nickoe> I was expecting to see the data in the beginning of main_ram, where the demo.bin is dumped, and I also tried the data I put at 0x41000000 via boot.json
<nickoe> main_ram : Origin: 0x40000000, Size: 0x04000000, Mode: RW, Cached: True Linker: False
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<thorns514> hi folks - I'm trying to track down some strange errors in my numato mimas a7 - what does it mean if the post-reset memory test in the LiteX bios console sometimes passes and sometimes fails?
<thorns514> (I've had a probably-unrelated problem of being unable to program this board over JTAG with a digilent cable, but only when on USB power)
<nickoe> maybe the memory is mis configure, maybe your power supply is wonky?
<thorns514> it seems to be about 50:50 even with the power supply disconnected and running off of USB power
<nickoe> does it work stable for other boards/people. I am not really familiar with the board
<thorns514> yeah I don't know, the example came from the manufacturer https://numato.com/kb/running-micropython-on-mimas-a7-using-litex-and-migen/ so I presume I wasn't supposed to have to go research sdram timings
<tpb> Title: Running MicroPython on Mimas A7 using LiteX and Migen | Numato Lab Help Center (at numato.com)
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