_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<_florent_> geertu: nice! Thanks for sharing, if you identify limitations while playing with featherwing extensions we could try to improve this.
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<geertu> _florent_: sure, will do
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<zyp> _florent_, possibly related: I'd like a way to do something like add_extension() that adds connectors
<zyp> consider e.g. the butterstick with syzygy connectors, and then you plug a syzygy to pmod adapter board into one
<geertu> zyp: That's a bit different, as unlike Featherwings, there is no standard w.r.t. signals on syzygy connectors (or is there?)
<zyp> there's some, but those are more fpga-oriented like clock capability and differential pair polarity/capability
<zyp> but I was thinking more in the sense of boards attached to boards so you get several levels of pinout mappings
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<Melkhior> @somlo Trying to stress-test the sdcard in buildroot (to see if I can reproduce the issue I have with Yocto), so far it's doing good; I've created a buildroot with more packages and cross-compiled binutils/gcc in it, then rebuilt a small numerical code in it and ran it with no issue.
<Melkhior> Now I'm pushing the sdcard a bit more: added a 128 MiB swapfile, and started the numerical code with a test case requiring ~330 MiB (the board has 256 MiB) under 'screen'.
<Melkhior> So far it hasn't crashed, step 1 is correct (roughly 40x slower than from memory), and I can disconnect from screen, run 'top' for a while, and reconnect screen ; it's very, very slow - but it doesn't crash:-)
<Melkhior> The only other device I use is the serial port for my console, no idea why Yocto is completely unreliable with the exact same kernel/dtb
<Melkhior> Maybe I should try disabling the [currently not working in Linux] Ethernet in the gateware - Yocto probably try to use it when buildroot just ignore it...
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<dormito> For a Litex project: If I have two module wrappers, is there any guides/turials that cover basic things like routing an output from one module ot the input of another?
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<somlo> Melkhior: interesting point -- I tried building the bitstream without ethernet support. I get the same hard lock-up when I try using multi-block sdcard write commands from linux
<somlo> at least the problem's symptoms don't change with what should be unrelated gateware being present or not...
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<thorns> hi folks - trying to extend a target for the first time, and I have a total noob question - I can't figure out how radiona_ulx3s.py (the target) is connected to radiona_ulx3s.py (the platform)?
<thorns> I see I import ulx3s from litex_boards.platforms but in the ulx3s.py platform I see no mention of that namespace or whatever it is...
<thorns> I see that I create ulx3s.Platform, which makes sense, but again I don't know where that namespace comes from
<thorns> nm I see there's some magic in litex_boards/__init__.py I think this is the connector