#litex on 2021-04-18 — irc logs at freenode.irclog.whitequark.org

2020-02-07 11:13 _florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex

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11:40 <lkcl> _florent_, something like this?

11:40 <lkcl> https://git.libre-soc.org/?p=pythondata-cpu-libresoc.git;a=summary

11:40 <tpb> Title: git.libre-soc.org Git - pythondata-cpu-libresoc.git/summary (at git.libre-soc.org)

11:45 <lkcl> i based it on vexrisc principle due to the massive source code size (130,000 lines of nmigen across multiple repositories)

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18:32 <lkcl> we use JTAG TAP (by Chips4Makers) in Libre-SOC, and it's very handy to connect to a running simulation using jtagremote

18:33 <lkcl> this is a patch which enables jtagremote, and adds a new option --with-jtagremote to the litex sim.py

18:33 <lkcl> https://ftp.libre-soc.org/litex-sim-jtagremote.patch

18:51 <chmouss> I'm trying to get etherbone to work on the Versa5G (lattice_versa_ecp5.py --with-etherbone --build). So far, the ping is OK, but litex_server can't connect.

18:52 <chmouss> Anyone had etherbone working on this board?

19:10 <lkcl> chmouss: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_server.py

19:10 <lkcl> that looks like quite a lot of options.

19:11 <lkcl> what options did you give?

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19:49 <chmouss> lkcl: basically litex_server --udp

19:50 <chmouss> I also gave the --udp-scan option a shot (did not find any etherbone); and also wishbone-toola shot: no luck

19:51 <lkcl> chmouss, can i recommend running tcpdump (or wireshark)?

19:52 <lkcl> see what's actually going on, whether there's traffic in/out

19:52 <_florent_> chmouss: Hi, IIRC I tested it recently on the Versa ECP5, but could do another test tomorrow

19:52 <_florent_> chmouss: Are you using up to date LiteX?

19:55 <_florent_> chmouss: can you check you are using a version after https://github.com/enjoy-digital/litex/commit/5af8e5c9345053763f6d89764790a7fc8793b8bf#diff-4e0251b978de9f85f279e2d5756bcf337447d4f18b4e6b02d77f94e1a709cb38?

19:56 <_florent_> chmouss: before this, the UDP/IP core was not running in the right clock domain due to a regression and required a sys_clk >= 125MHz

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20:00 <chmouss> _florent_: I tried both the 2020.12 and master revisions; I can see that the timings are muich harder to close on master but same behaviour for either revisions

20:00 <chmouss> I'm using trellis though, not sure if it could have an impact

20:00 <_florent_> chmouss: OK, I'll do a test tomorrow

20:01 <chmouss> bty, I also had the same behaviour with a RMII 100Mbps PHY, ping OK pour etherbone don't respond

20:01 <chmouss> I can send you the wireshark traces if you wish

20:07 <_florent_> chmouss: I'll first do a test and will share the bistream with you if working on my side.

20:18 <chmouss> thanks!

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