05:03 <tcal> cjearls: You might want to start with a straight LiteX install and build the OrangeCrab target. Start here: https://github.com/enjoy-digital/litex#quick-start-guide, and at step 4, your command will be something like `./gsd_orangecrab.py --cpu-type=vexriscv --cpu-variant=minimal --build --flash`. It will create an ACM device that you can connect to using lxterm or picocom. It will be very similar to Fomu or Icebreaker

05:03 <tcal> -- I wrote up some stuff about Fomu here: https://tcal-x.github.io/Fomu-Donut/

05:03 <tpb> Title: Doing Donuts with Fomu – tcal-x – FPGAs -n- stuff (at tcal-x.github.io)

05:12 <sajattack[m]> _florent_: I'm having a hang here, any idea what I'm doing wrong?

05:12 <sajattack[m]> https://hatebin.com/ezjwdbyfsg

05:12 <tpb> Title: hatebin (at hatebin.com)

05:16 <tcal> cjearls: I hadn't noticed earlier -- the orangecrab board is mentioned in this tweet: https://twitter.com/enjoy_digital/status/1341095343816118272 (there was a recent name change orangecrab.py --> gsd_orangecrab.py). So try using that build line.

05:42 <sajattack[m]> I'm not seeing a memory region for the spi flash in my svd, maybe this is a problem?

13:48 <thorns514> I got my verilog peripheral working in litex! so cool

13:51 <thorns514> after fixing up my wishbone slave a little, the only remaining issue was figuring out the correct order/parameters to create a new IO memory region. seems like that has changed a lot recently so a lot of what I found on the internet wasn't quite right ...

15:40 <thorns514> in wishbone B3, litex specifically, is a slave allowed to respond to asserted STB if CYC de-asserted? I think this one of my bugs in my slave - requiring CYC && STB fixed it, but I thought one could rely on a master never asserting STB without CYC ...

17:28 <Bleepshop> Oh good, there's enough people here I'm probably not the only one playing with an RV901T.

17:31 <zyp> thorns514, spec states: SLAVE interfaces MAY NOT respond to any SLAVE signals when [CYC_I] is negated.

17:31 <zyp> also: MASTER interfaces initiate a transfer cycle by asserting [CYC_O]. When [CYC_O] is negated,

17:31 <zyp> all other MASTER signals are invalid.

17:52 <thorns514> zyp, thanks I guess that ought to be read "MUST NOT"

17:55 <zyp> that's how I read it, yes