<nickoe>
signal wire defined as Subsignal("cw", Pins("L3"), IOStandard("LVCMOS33")),
<nickoe>
I would expect led and dac_cw to be in phase.
<_florent_>
nickoe: GTKwave allow you to shift signals, you probably did it unintentionally, you can just remove the signals and add them again
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<nickoe>
ohh, puhh, good! I thought something was annoying and inexplicably out of wack!
<nickoe>
Can I do LiteDRAMDMAReader -> AXIStreamInterface -> dac_plat? ?
<nickoe>
or I have a verilog module that is supposed to take some axi interface and do the correct thing on the "dac_plat" output pins, https://dpaste.com/BXWEKN6RZ.txt
<nickoe>
(that someone else wrote on my "team")
<nickoe>
for that verilog file wiht "#(parameter IN_DATA_WIDTH=20)" can I specify that in the Instance()?
<nickoe>
or is that p_?
<nickoe>
prefix
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