10:01 <geertu> Aha, arty builds with microwatt

10:01 <geertu> The trick is --cpu-variant=standard+irq

10:02 <geertu> But then the OC build fails due to "ERROR: No such command: read_vhdl", as Yosys doesn't do VHDL yet?

10:55 <geertu> Hmm, use_ghdl_yosys_plugin?

10:59 <geertu> --cpu-variant=standard+ghdl

10:59 <geertu> ERROR: This version of yosys is built without plugin support.

10:59 <geertu> Wish I had read https://github.com/enjoy-digital/litex/issues/245 _until the bottom_ before

14:00 <Melkhior> @geertu is microwatt complete enough to run an operating system yet, or is it just for some baremetal codes ATM ?

14:01 <Melkhior> I wish I could use a SPARC CPU like LEON with LIteX, might be able to build a fast buildhost for pkgsr in NetBSD/sparc :-)

14:01 <Melkhior> s/pkgsr/pkgsrc/

14:37 <geertu> Melkhior: It should be

14:37 <geertu> Leave out the "fast" part ;-)

15:04 <Melkhior> @geertu for microwatt certainly not fast (my G5 Quad would be tough to beat in an affordable FPGA;-)  ), but for 32-bits SPARC you only really need to outrun a couple of 60 MHz SuperSPARC (SM61) or some 100-150 MHz HyperSPARC ; might be achievable in reasonable FPGA for integer workload such as compiling... currently I/O is a big issue (Qemu

15:04 <Melkhior> smokes the real hardware), followed by memory (at most 512 GiB in a SS20) and then CPU (which Qemu beats, but currently it can only emulate a single core).

15:04 <Melkhior> I suspect that if you could fit a couple of LEON with a minimalist FPU in an Artix-7 (100k?) with litesata & liteeth and at least 512 MiB, it would compile faster than a dual-SM61 system - assuming you can port NetBSD to it, that is :-)

15:04 <Melkhior> looking forward to linux-on-litex-microwatt:-)  :-)

15:05 <leons> I knew this CPU would haunt me because of the name at some point! It all starts with IRC notifications :)

15:05 <Melkhior> @leons sorry :-)

15:05 <leons> But actually, I'd be very happy about LEON CPUs in LiteX as well! Even if it's just for experimenting

15:05 <leons> Melkhior: no worries, just joking around :)

15:08 <Melkhior> Would love to try LEON, but I've found nothing as easy-to-use as LiteX for it ... the grlib/Cobham Gaisler stuff is way too complicated for me, and the other open-source SoC supports higher-end (read: more expensive) FPGA boards

15:09 <Melkhior> e.g. https://www.esp.cs.columbia.edu/

15:09 <tpb> Title: ESP - open SoC platformESP | ESP - open SoC platform (at www.esp.cs.columbia.edu)

15:18 <Melkhior> Cheapest board I see a constraint file for is the Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit, and that's $2.5k already... the VCU128 is $9k

15:18 <Melkhior> It's a bit expensive just to try LEON...

15:19 <Melkhior> so, sticking with VexRiscv & looking into packed simd ('P') at the moment

15:21 <leons> Melkhior: holy smokes. Yeah, I'm really happy that I can do VexRiscv with PMP + quite a few LiteX cores + LiteEth + some custom cores and it fits in my ~100€ budget

15:21 <leons> (with the Arty A7 35T)

15:23 <Melkhior> @leons Yes it's an impressive piece of SW

15:23 <Melkhior> But i've added too many instructions in VexRiscv (somewhat naively so I'm probably wasting space), dual-core is starting to feel restricted ib my 35k Artix-7...

15:23 <Melkhior> It's just too easy to play with, now I want more :-)

15:24 <leons> that's the benefit of a single-threaded OS, there's only so much complexity your CPU will reasonably need :)

20:42 <Finde> Melkhior: there's a gsoc idea for FOSSi of connecting openpiton to litex, which could enable the opensparc t1 :p