_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
Dolu has quit [Ping timeout: 246 seconds]
lf_ has quit [Ping timeout: 240 seconds]
lf has joined #litex
Degi has quit [Ping timeout: 256 seconds]
Degi has joined #litex
<a314> I'm running into a "assert c.size <= busword" (~line 500 of csr.py) failing when trying to import litespi into a design
<a314> the CSR bus is 8 bits data, 14 bits address, but i tried raising it and that didn't seem to help
<zyp> you tried raising what?
<zyp> looks like the rxtx CSR defaults to 32 bits wide, which is not gonna fit on an 8 bit wide bus
Bertl_oO is now known as Bertl_zZ
Dolu has joined #litex
iTitou has joined #litex
<iTitou> Hello everyone ! I'm new to LiteX (and fpga development in general). I'm trying to make a simple design with CSRs (https://github.com/titouanc/fpga-scratchpad/blob/master/03-CSR.py) but I don't see my CSRs in the generated CSV (http://paste.awesom.eu/51uz)
<tpb> Title: Paste it § (at paste.awesom.eu)
TMM has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM has joined #litex
Bertl_zZ is now known as Bertl
a314 has quit [Ping timeout: 260 seconds]
ambro718 has joined #litex