_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<Melkhior> Hello all! Just to say I'm impressed how easy its is to use Litex. I've added the Zbp subset of 'B' to Vexrisc (<https://github.com/SpinalHDL/VexRiscv/pull/148>), it works, and the Chacha20 crypto algorithm is 30% faster from being able to use the rotation instruction :-)
<Melkhior> And I'm a SW guy, HW is new to me...
<Melkhior> Thanks for it and kudos :-)
<_florent_> Melkhior: great! thanks for the feedback
<sorear> in the current draft, rori is in Zbb which might be less resources
<_florent_> a314: strange for your UARTWishboneBridge issue, are you using anything specific?
<Melkhior> sorear True, but Zpb also has grev which can be useful to handle endianess issue or bit-reversal...
<sorear> > (such as “Zbb” implements rev8 and rev, which are pseudo-instructions for grevi rd, rs1, -8andgrevi rd, rs1, -1 respectively
<Melkhior> sorear Also Zbp doesn't have 'partial' instruction (Zbb has rev8 and rev but not the other), I wouldn't have known how to implement that... so I did the easier subextension for me :-)
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<a314> _florent_: I tried both with SRAM and CSR -> GPIOOut
<a314> the only weird thing I'm doing is building to verilog and then feeding that into yosys -> nextpnr, instead of using the Platform
<a314> but I tried adding my own wishbone master (wrapped in Instance) and it worked perfectly, so I'm very confused
<daveshah> Your design is meeting timing?