16:08 <acathla> xobs, I need your help with wishbone-tool and the protocol over uart. I try to write something in C and I try to understand the protocol.

16:09 <acathla> When I do wishbone-tool 0x12345678, It sends over the serial port : 0x02 01 04 8D 15 9E

16:09 <xobs> acathla: it's late here, so I don't know that I'll be up much later. But probably what you want is `wishbone-tool -s wishbone --uart /dev/ttyUSB0`, which will start up a wishbone server on port 1234.

16:09 <acathla> 02 is the command, 01 is the size

16:09 <xobs> Then you can use https://github.com/litex-hub/wishbone-utils/tree/master/libeb-c to write something in C.

16:09 <acathla> I'm sure you have the simple anszer

16:09 <xobs> Or... let's see, what protocol is it using...

16:10 <acathla> Why would the address be so... strange, and not the data.

16:11 <xobs> It's shifted left by two bits, because Wishbone is a 32-bit bus.

16:11 <xobs> Er, shifted right.

16:11 <xobs> https://github.com/litex-hub/wishbone-utils/blob/master/wishbone-tool/crates/bridge/src/bridges/uart.rs#L282-L288

16:17 <acathla> Hum, there should be something else, endian conversion or something. Thanks

16:21 <xobs> Yes, addresses are big endian.

16:32 <acathla> Oh, ok, I was just reading the bits in the logic analyzer and it's LSB first

16:33 <Krickit> hi everybody, can you tell me what are mem.init, mem_2.init and mem_1.init generated ?

18:21 <somlo> Krickit: they are binary blobs representing the bios (mem.init) and a few other memory regions that should be built into the fpga bitstream for when the SoC "wakes up" after being programmed into the fpga

18:23 <somlo> oh well, he's disconnected :)