08:18 <_florent_> Finde: Ariane (CVA6 now: https://github.com/openhwgroup/cva6) would indeed be an interesting CPU to support, I've also been thinking about it, there will probably be opportunities to add support for it next year

08:22 <_florent_> daveshah, somlo: not sure I followed exactly the issue you are looking at, but if you think it could be related to LiteX, happy to help (on monday)

08:23 <daveshah> No, it's definitely a synthesis bug

08:24 <_florent_> ok, thanks

09:45 <daveshah> great, I've reproduced the problem using litex_sim hacking the build script to run a Yosys opt pass

09:45 <daveshah> now I can compare the vcds and find exactly which signal is going wrong

09:46 <daveshah> there's no address bus activity at all with broken Yosys

09:46 <daveshah> so something has definitely gone horribly, horribly wrong

10:45 <daveshah> ugh, I think the problem isn't actually in Yosys but some UB in Rocket/its glue (a debug register that is never clocked, reset or initialised now being validly optimised to x rather than 0)

10:46 <daveshah> unfortunately, finding out where those clock/resets should be coming from is a bit tricky

11:01 <daveshah> somlo/_florent_: the following monkey-patch fixes the above UB by tying async reset to 1 so the FFs are kept at 0 instead of being undefined

11:02 <daveshah> https://www.irccloud.com/pastebin/bVDYvlwo/

11:02 <tpb> Title: Snippet | IRCCloud (at www.irccloud.com)

11:02 <daveshah> i'll leave it up to you as to whether this needs to be fixed by changing how the debug signals are tied in the LiteX Rocket glue, or whether there is a problem in Rocket itself

11:03 <daveshah> (note that patch is for a minimal, not Linux, config but it was just about testing things as quickly as possible, I don't think it's the right fix anyway)

11:11 <daveshah> never mind, ignore that patch, I had some other stuff in my tree that was messing things up

11:18 <daveshah> somlo/_florent_: sorry for all the noise. ignore the previous diff, here is a proper patch that seems to work. https://github.com/enjoy-digital/litex/pull/713

13:14 <somlo> daveshah, _florent_: I merged 713, as it does indeed fix litex+rocket when using the new yosys

13:14 <somlo> daveshah: thanks a ton for tracking this down!

13:14 <daveshah> great, thanks for confirming!

13:14 <daveshah> no problem

23:13 <cjearls> Hi, I'm doing some Verilog digital design on Linux, and I was hoping that someone would be able to direct me to some good tools for waveform viewing and debugging. For a while, I have been using ModelSim in a Windows VM, but I'd prefer all my tools to run natively on Linux. I tried using Verilator to dump waveforms, then GTKWave to view them, but it didn't seem as easy to use as Modelsim. Do you have any recommendations for a good combination

23:13 <cjearls> of tools?