_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<_florent_> Finde: Ariane (CVA6 now: https://github.com/openhwgroup/cva6) would indeed be an interesting CPU to support, I've also been thinking about it, there will probably be opportunities to add support for it next year
<_florent_> daveshah, somlo: not sure I followed exactly the issue you are looking at, but if you think it could be related to LiteX, happy to help (on monday)
<daveshah> No, it's definitely a synthesis bug
<_florent_> ok, thanks
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<daveshah> great, I've reproduced the problem using litex_sim hacking the build script to run a Yosys opt pass
<daveshah> now I can compare the vcds and find exactly which signal is going wrong
<daveshah> there's no address bus activity at all with broken Yosys
<daveshah> so something has definitely gone horribly, horribly wrong
<daveshah> ugh, I think the problem isn't actually in Yosys but some UB in Rocket/its glue (a debug register that is never clocked, reset or initialised now being validly optimised to x rather than 0)
<daveshah> unfortunately, finding out where those clock/resets should be coming from is a bit tricky
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<daveshah> somlo/_florent_: the following monkey-patch fixes the above UB by tying async reset to 1 so the FFs are kept at 0 instead of being undefined
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<daveshah> i'll leave it up to you as to whether this needs to be fixed by changing how the debug signals are tied in the LiteX Rocket glue, or whether there is a problem in Rocket itself
<daveshah> (note that patch is for a minimal, not Linux, config but it was just about testing things as quickly as possible, I don't think it's the right fix anyway)
<daveshah> never mind, ignore that patch, I had some other stuff in my tree that was messing things up
<daveshah> somlo/_florent_: sorry for all the noise. ignore the previous diff, here is a proper patch that seems to work. https://github.com/enjoy-digital/litex/pull/713
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<somlo> daveshah, _florent_: I merged 713, as it does indeed fix litex+rocket when using the new yosys
<somlo> daveshah: thanks a ton for tracking this down!
<daveshah> great, thanks for confirming!
<daveshah> no problem
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<cjearls> Hi, I'm doing some Verilog digital design on Linux, and I was hoping that someone would be able to direct me to some good tools for waveform viewing and debugging. For a while, I have been using ModelSim in a Windows VM, but I'd prefer all my tools to run natively on Linux. I tried using Verilator to dump waveforms, then GTKWave to view them, but it didn't seem as easy to use as Modelsim. Do you have any recommendations for a good combination
<cjearls> of tools?