_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<Bertl> does LiteX play nice with nMigen?
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<_florent_> Bertl_zZ: LiteICLink provides the TX/RX GTP init sequences and generic GTP/GTPQuadPLL code that can be used used as a basis for several protocols
<_florent_> Bertl_zZ: depenting the protocols, like SATA here, the parameter are then adjusted using the parameters from the Xilinx wizard
<_florent_> for now it's not possible possible to mix Migen/nMigen code directly, but you can already use verilog to instantiate Migen/LiteX code in nMigen or the opposite
<_florent_> that's what we are doing for example for the Minerva CPU: the verilog instance: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/minerva/core.py#L55-L90
<_florent_> but for LiteSATA, i'm planning to provide you a standalone verilog core, so that would be the opposite if you want to use nMigen for the integration: integrate the litesata standalone core as a verilog module in nMigen
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<teknoman117> are there any specific requirements for running litepcie at a 128 bit data width versus a 64 bit data width? I'm trying to set up LiteX on the RHS Research LiteFury, which is very similar to the Numato Aller (a board in the litex-boards repo).
<teknoman117> I've gotten all of the litepcie tests to work with a 64 bit data path, but if I switch it to 128 bit, all the systems I try to plug the board into fail to post, or if they do, hang at Linux boot.
<teknoman117> (changing "data_width" from 64 to 128)
<teknoman117> The FPGA does come up, I see the LedChaser on the user leds working