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<Bk>
Hi everybody! I have to connect my IP with axi-lite bus. I have generate a risc-v with cpu pico32 and bus axi-lite in my zybo board, but when I create a project in vivado i don't understand how to connect risc-v with my Ip. Can everyone help me?
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<Bk>
Hi everybody! I have to connect my IP with axi-lite bus. I have generate a risc-v with cpu pico32 and bus axi-lite in my zybo board, but when I create a project in vivado i don't understand how to connect risc-v with my Ip. Can everyone help me?
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<leons>
Is there any specific reason why the CSR data width is defaulting to 8-bits? Intuitively this makes SW run slightly slower and I don't see any HW benefits (yet).
<zyp>
wasn't the default recently changed from 8 to 32?
<leons>
zyp: Oh, I see the commit. I was using an older release, hence my default was still 8.
<leons>
And the commit message explains that there is no negative impact, great!
<Bk>
anyone can help me?
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<mithro>
@leons Wider buses are harder to route on an FPGA
<mithro>
@leons as the CSR bus goes all over the FPGA (to pretty much every peripheral), it can be a driver of congestion
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