<dkozel>
_florent_: The Siglent oscilloscope is a fun new platform! Is there a specific project around that? Seems like a huge amount of work still needed to make that work well.
<daveshah>
It's telling of the kind of volume discounts they must be getting, at retail the FPGA alone would be ¼ the price of the scope
<dkozel>
Volume prices on ICs really bend my mind
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<_florent_>
dkozel: thanks, the pinout is from https://github.com/360nosc0pe and i wanted to see for quite some times if we could run LiteX on it
<_florent_>
for now the Ethernet/DRAM is working (so already Linux capable) and i'd like to get at least the LCD/Buttons/Leds working and then the ADC
<_florent_>
some work had already started on that in 360nosc0pe project (it was also LiteX based but only for the peripherals of the Zynq)
<_florent_>
After that, creating a full standalone scope is indeed a massive work, i'm not planning to work on that, but with just the SoC + ADC support it would be nice to add glscopeclient support
<dkozel>
In a Zynq can LiteX use the hard processor and expose the HDL peripherals to it?
<_florent_>
dkozel: that's indeed the purpose of zynq7000/core.py. I don't use it that much personally but i did for some clients that are running Linux on the Zynq and create the SoC/Peripherals with LiteX.
<dkozel>
So cool. I want a weekend to look at that. Do you have any idea of the max data rate that can be streamed across the interface?
<dkozel>
Have you ever looked at the ADALM PLUTO SDR?
<_florent_>
dkozel: for the AXI GP we are converting to to AXI Lite when connecing it the main LiteX bus, so that's good for control/status
<_florent_>
the AXI HP is AXI FULL, so the limitation is the Zynq here
<_florent_>
I just ordered an ADALM PLUTO a few weeks ago :) but haven't played with it yet. We could add it as a LiteX-Boards platform if you want
<_florent_>
i also have a simple LiteX AD9631 PHY
<_florent_>
daveshah: in case you have 2 min, would you mind having a look at: https://github.com/enjoy-digital/litex/pull/696 (ie is passing the idcode of ECP5 12F variant to NextPnr still required?)
<daveshah>
_florent_: no, if you use --12k you don't need the --idcode ecppack param too
<daveshah>
--12k to nextpnr is the recommended route now
<_florent_>
ok good, that's what we are already doing in LiteX, so the PR is not needed, thanks.
<daveshah>
oops snap we both responded!
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<_florent_>
daveshah: ah sorry, thanks.
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<dkozel>
_florent_: It would be extremely cool to see even the most basic demo of a LiteX build for the Pluto that has the AD9631 included.
<dkozel>
I was looking at ordering the JTAG adapter for the Pluto, but probably will just solder on some wires
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<teknoman117>
hello all, I only discovered LiteX recently and have been trying to bring up various components on an Alchitry Au (part: xc7a35t-ftg256-1) I got recently. I'm currently quite stuck with the onboard DDR3. At this point I have it working via Vivado and MIGv7, so I know the module is functional. I mirrored the mimas_a7 target from litex-boards, and I
<teknoman117>
have some CSR registers I can control via wishbone-tool over a uart (minisoc). I believe I set up my pins correctly (they match the xdc file generated by vivado). However, when I load the gateware, if I write more data via wishbone-tool than the L2 cache is configured for, the older locations just revert to "0".
<teknoman117>
the sys_clk_freq was reduced to 83.333 MHz since the -1 speed grade artix-7's can only do 667 Mb/s per pin for DDR3L. (does reducing sys_clk_freq drop the DRAM frequency?)
<teknoman117>
just looking for some guidance, not really sure where to start debugging
<daveshah>
I'm not really familiar with using wishbone tool instead of an embedded CPU, but do you get some kind of DDR initialisation output?
<teknoman117>
you know, I haven't tried an embedded cpu at this point (was trying to take baby steps), so if there are initialization steps to start the ddr3 module that's definitely not being done
<daveshah>
Initialisation is definitely required, for example to calibrate the delay primitives and set up the control regs in the RAM
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<teknoman117>
I switched to using a soft-cpu (this was way too easy lol)
<teknoman117>
is there any way to use the 1:2 clocking on the Artix-7? If I try to change all the sys4x clocks to something like "sys2x" i get errors about unresolved clock domains