04:51 <Bertl_oO> Greetings! I'm getting 'OSError: Unable to find or source Vivado toolchain' despite export LITEX_ENV_VIVADO=/opt/Xilinx/Vivado/2020.1/

04:51 <Bertl_oO> any idea what is wrong here?

06:07 <_florent_> Bertl_oO: Hi, can you try with source /opt/Xilinx/Vivado/2020.1/settings64.sh before running the script?

06:08 <_florent_> Bertl_oO: i'll do a check with export this morning

06:08 <Bertl_oO> yep, that works

06:11 <_florent_> ok thanks

06:26 <Bertl_oO> _florent_: btw, why do you import generic_platform a second time in https://github.com/enjoy-digital/litesata_axiom/blob/master/litesata_axiom.py#L14

06:32 <_florent_> Bertl_oO: strange it seems to have disappeared... https://github.com/enjoy-digital/litesata_axiom/blob/master/litesata_axiom.py#L12 (thanks :))

06:34 <Bertl_oO> _florent_: okay :) and what does the -1 in S7PLL(speedgrade=-1) mean?

07:00 <_florent_> Bertl_oO: that we are using the -1 speedgrade timings for the PLL, which i'm using by default since will also works on a -2 or -3 speedgrade.

07:00 <_florent_> Bertl_oO: it just affects the max VCO freq: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/clock/xilinx_s7.py#L23-L27

07:01 <Bertl_oO> okay, so that could/should? also be -2 on this specific board, yes?

07:06 <_florent_> you can set it to -2 yes, using -2/-3 just allow more flexibility in the generated frequencies

07:07 <Bertl_oO> understood, tx

07:09 <Bertl_oO> is adding self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]") to Platform's _init_(): the correct way to fix the warnings about the config voltage (and similar for CFGBVS)?

07:11 <Bertl_oO> and in https://github.com/enjoy-digital/litesata_axiom/blob/master/litesata_axiom.py#L92 what does the bscan_spi_xc7a200t.bit mean?

08:07 <_florent_> Bertl_zZ: yes correct for the config voltage warning

08:09 <_florent_> Bertl_zZ: the bscan_spi_xc7a00t.bit is used to flash the bitstream in SPI Flash with OpenOCD, since we are just testing things here and loading the bitstream to SRAM, it's not useful

09:50 <hexastorm> build a controller for a laser scanner with Litex and Migen see https://youtu.be/EAEqUILP_fo

09:50 <hexastorm> uses SPI to stream over data and project it with the laser... not perfect but it does work :-)...

10:01 <_florent_> hexastorm: Hi, very nice, thanks for sharing! It's really motivating to see such projects created with the tools/framework. I'll have a closer look at it

10:03 <hexastorm> thanks it is a great framework... still have much to learn, but your tools have made it a lot easier...

14:45 <_florent_> Bertl_zZ: the use of LITEX_ENV_VIVADO is now fixed by https://github.com/enjoy-digital/litex/commit/444a605deae6a561dbe2c49bf3062eae6f3cd887

14:45 <_florent_> Bertl_zZ: sorry i broke it while adding the error messages with https://github.com/enjoy-digital/litex/commit/db836e8e5d9d66caade9294f1a8b67eb2b4d3611

16:16 <Bertl> _florent_: thanks! works now!

16:17 <Bertl> is there some documentation regarding the LiteSATA IP I could read up on?

16:56 <cjearls> I have a question about using a custom build of VexRiscv for Linux-on-Litex-Vexriscv:

16:58 <cjearls> Once I've correctly generated a new VexRiscv core with the hardware that I wanted to add, how do I add it to the linux-on-litex-vexriscv directory such that it is built instead of the default vexriscv core?

16:59 <cjearls> Also, is there a way to tell what the settings are for the default vexriscv core that's used for Linux-on-LiteX? I want to be sure I'm not removing anything important, just that I'm added the hardware I'm interested in

17:10 <zyp> I'd guess this is what generates the cores: https://github.com/litex-hub/pythondata-cpu-vexriscv/blob/master/pythondata_cpu_vexriscv/verilog/Makefile

17:10 <zyp> and then litex picks one of those depending on what options you select

17:11 <zyp> ref. https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py#L23

17:24 <daveshah> https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L103 is where the variant is set in linux-on-litex

17:30 <cjearls> So if I want to add code to VexRiscv to define a new plugin, then to enable that plugin, where would that happen?

17:31 <cjearls> Is there somewhere I should be checking for this information or a description of the build process? I don't want to be wasting anyone's time with really basic questions if I can be finding the answer myself

17:33 <zyp> I figure that since litex only deals with prebuilt .v files, you can build your own .v in whatever manner you like and then either overwrite one of the existing .v files or add a new variant

17:36 <_florent_> cjearls: to use a custom Vexriscv.v, you can also use use_external_variant: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py#L264

17:36 <_florent_> cjearls: that's what is used in Foboot or Betrusted to use a custom variant of VexRiscv IIRC

17:39 <_florent_> cjearls: https://github.com/betrusted-io/betrusted-soc/blob/master/betrusted_soc.py#L1284

17:40 <_florent_> https://github.com/im-tomu/foboot/blob/master/hw/foboot-bitstream.py#L264

17:40 <_florent_> with the custom CPU here: https://github.com/im-tomu/foboot/tree/master/hw/rtl

17:42 <cjearls> _florent_: Thank you, that was very helpful, I wasn't sure how use_external_variant would be utilized, but it makes sense now, it's a file path to the variant

17:49 <_florent_> Bertl: sorry there is not that much documentation for now, i'm planning to write some to ease your integration

18:04 <Bertl> _florent_: okay, no problem ... where did the gtp_params in a7sataphy.py come from, i.e. how did you figure out the various settings there?