_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<lkcl> _florent_, daveshah: do you happen to know if the litex L2 cache granularity can be set to byte-level select lines?
<lkcl> Staf needs to do a fixed-arrangement for the ASIC SRAM blocks and he has time only for one
<lkcl> we picked 64-bit wide, 1k total, 8x byte-level select lines
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