00:11 <kbeckmann> it would seem that what i am trying to do is not possible. when trying to place the second PCIe PHY IP, i am informed by vivado that it can only be placed at location X0Y0, so i guess there is only room for one. looks like i'd have to use a Virtex to do this according to some other information i found... oh well, was worth a try.

05:52 <a314> what's the difference between nmigen-soc and litex for things like wishbone Records? are they designed to be cross-compatible or should I use LiteX's infrastructure if I want to use LiteX cores

07:46 <_franck_> kbeckmann: https://github.com/fjullien/pcie_analyzer/blob/master/ac701.py#L282

07:55 <_florent_> kbeckmann: sure you can ask LiteX/NeTV2 questions here, the NeTV2 target in LiteX-Boards does not has PCIe, but i should add it

07:58 <_florent_> kbeckmann: otherwise Artix7 only have 1 PCIe hardblock, so that's not possible to use the PCIe PHY from Xilinx for your use case

08:01 <_florent_> kbeckmann: it should be possible to do so something by manually instantiating the GTP transceivers (eventually reuse LiteICLink to ease things: https://github.com/enjoy-digital/liteiclink), but you'll still probably need a PCIe PHY

08:07 <_florent_> The approach with _franck_'s PCIe Analyzer is probably easier since uses a PCIe interposer to snif the TX/RX lanes , but does not allow injection.

08:09 <_florent_> powergraphic[m]: i'm still working on LiteSATA integration, but the current code can be found here:

08:10 <_florent_> https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1428-L1468

08:10 <_florent_> https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/kc705.py#L89-L122

08:11 <_florent_> For now it's read only and allows booting binaries from a FAT SSD/HDD

08:16 <_florent_> a314: you should indeed use LiteX's infrastructure with LiteX cores. It's probably possible to create mixed SoC with nmigen-soc/LiteX, but for this you'll probably pass by verilog and rely on the bus standards (Wishbone, AXI, etc...)

08:19 <_florent_> st-gourichon-fid: i could have a look at the flash issue, would you mind creating an issue with a minimal repro on github for the Fomu (for example since i think you are using this board).

08:27 <kbeckmann> _florent_, _franck_: thanks for your replies! yeah for just sniffing and repeating the TLPs, fjullien's approach is nice. i want to be able to reject/modify/insert my own TLPs though, which is why i need a protocol implementation that handles the Data Link Layer and Physical Layer for me. eventually i want to use an open source implementation of this but it doesn't exist yet afaik. this project is

08:27 <kbeckmann> ongoing but in a quite early stage https://codeberg.org/ECP5-PCIe/ECP5-PCIe

08:27 <tpb> Title: ECP5-PCIe/ECP5-PCIe: A PCIe interface for the ECP5 FPGA written in nMigen - ECP5-PCIe - Codeberg.org (at codeberg.org)

08:30 <kbeckmann> and eventually i also want to do this project with an ECP5. but i thought it would be nice to get started with this using an fpga that has proper PCIe support. one way to do what i want to do is to use two FPGA boards - one upstream and one downstream. it gets a bit clunky but should work.

08:34 <_franck_> kbeckmann: do you want to have one FPGA acting as a PCIe endpoint and the other as a Root complex ? Or to have both in the middle of a root<->endpoint link acting passively ?

08:40 <kbeckmann> _franck_: Ideally I want it to be transparent, so whatever the PCIe device i want to intercept is connected to - be it a root complex or a switch.

08:41 <kbeckmann> "pcie mitm" has been done before by quite a few folks, but afaict there isn't an off-the-shelf easy to use solution for this, which is what i would like to build. i know i'm in deep water here because i don't know much about this, but i want to try :D

08:43 <kbeckmann> oh and add "cheap" to that as well. i envision a project like this to have a BOM of < 200 eur or so.

08:44 <_florent_> kbeckmann: interesting, _franck_'s analyzer could be very useful to develop your project since would gives full visibility, coupling it with glscopeclient and a PCIe decoder would also be very nice :)

08:47 <kbeckmann> doh, connected the dots now that _franck_ is fjullien :). yeah for sure!

08:48 <_florent_> _franck_: just a question: i recently added write latency calibration support to LiteDRAM and think it could help for the calibration on AC701

08:48 <_florent_> _franck_: in case you a time, would you mind doing a test on the AC701, by replacing: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/ac701.py#L70

08:49 <kbeckmann> i want to have a decent scriptable interface where you can trigger and modify certain TLP signatures and so on, enable fuzzing, and a bunch of other stuff. but getting a good pass-through analysis is obviously also nice to have.

08:49 <_florent_> _franck_: with: pads = platform.request("ddram"), ?

08:51 <_franck_> _florent_: I'm planning to work again on the PCIe analyzer soon. I'll test your changes.

08:51 <_florent_> _franck_: perfect, thanks!

09:52 <st-gourichon-fid> _florent_ yes, a formal bug report is a good idea (takes some time still and can't do that today, am on something different).

09:55 <st-gourichon-fid> _florent_, will do it ASAP, thanks for your care!

18:27 <lkcl> folks i need to connect up 4 GPIO wires to a versa ecp5

18:27 <lkcl> https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/versa_ecp5.py

18:28 <lkcl> however unlike for ulx3s there isn't actually anything listed in the io platform as "gpio"

18:28 <daveshah> use the X3 connector

18:28 <lkcl> daveshah: ah. what's the voodoo magic incantation to get the _connectors?

18:29 <lkcl> platform.request("X3", 0") gives "error doesn't exist"

18:29 <lkcl> resource doesn't exist or something like that

18:30 <lkcl> i spent quite a lot of time going through the code and couldn't find a function which actually turns X3 into "resource"

18:31 <lkcl> the "hack" way of doing it would be to actually monkey-patch versa_ecp5._io :)

18:31 <daveshah> this is some random code I wrote a while ago for a similar problem

18:31 <daveshah> https://github.com/daveshah1/linux-on-litex-vexriscv/commit/dc97bac3aeb04cfbf5116a6c7e324ce849391770#diff-2353956cb1116676bd6b96769c8ebf7b4b86c16c47511eb2888d0dd2a979e09eR117-R134

18:31 <daveshah> hopefully that idea still works

18:31 <daveshah> the key is add_extension

18:31 <lkcl> ahh add_extension

18:31 <lkcl> nice. thank you

18:32 <lkcl> better than monkey-patching versa_ecp5._io :)

18:32 <lkcl> def add_extension(self, *args, **kwargs):

18:32 <lkcl> return self.constraint_manager.add_extension(*args, **kwargs)

18:32 <lkcl> yeah that should work perfectly, thank you daveshah

18:47 <lkcl> daveshah: brilliant, that works perfectly

18:47 <lkcl> much appreciated