17:39 <andrewb1999> Hi everyone! I'm just starting to get into Litex and I was wondering if there is a way to expose an axi lite interface as IO for the top level design. I am trying to interface a softcore with other axi IP that is not in migen.

18:05 <zyp> yeah, I believe there's adapters both to and from axi lite in here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/axi.py

18:05 <tpb> Title: litex/axi.py at master · enjoy-digital/litex · GitHub (at github.com)

22:35 <lkcl> i just heard on #nmigen that it may be possible to get litex to use nmigen's "migen compat" capability. i.e. route all use of migen in litex through nmigen.compat. is this correct?

22:36 <lkcl> one of the weaknesses of litex is its use of migen, which does no typechecking, relying on verilog to find errors.

22:36 <lkcl> it would be veeery good to be able to use nmigen.compat and to have nmigen do some type and other error checking.