07:16 <krickit> hi

07:21 <_florent_> hi

07:21 <_florent_> Krickit: which design are you trying to build?

07:22 <_florent_> st-gourichon-fid: DFU support is minimal yes, we could improve it

07:23 <krickit> i'm trying to design a circuit on versa ecp5 with ecp5 lattice fpga

07:24 <krickit> now i have this error

07:24 <_florent_> ok and are you starting from an existing litex target?

07:25 <krickit> nope i used the guide step by step

07:25 <krickit> now i have a gateware folder with verilog file, init memory files and pinmap

07:26 <krickit> i added che pico32 verilog file on my project

07:26 <krickit> i did't understand where i wrong

07:27 <_florent_> in the gui we recommend to use a litex target, can you describe which steps you followed? which script you are running?

07:28 <_florent_> are you running this? : https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/versa_ecp5.py

07:28 <krickit> yes, i used this link https://github.com/enjoy-digital/litex

07:28 <_florent_> if you select a PicoRV32 CPU, LiteX will automatically add it to the design for you (including the sources)

07:29 <_florent_> yes but this link is the LiteX repository :)

07:30 <krickit> yes in fact

07:30 <krickit> i went to folder litex_board - targets

07:31 <krickit> and i run versa_ecp5.py with option diamond toolchain

07:31 <_florent_> ok

07:31 <krickit> i work on ubuntu subsystem in windows 10

07:32 <_florent_> and it's stuck on "running DRC..."?

07:32 <krickit> yes

07:33 <krickit> when i try to syntetize

07:33 <krickit> with versa_ecp5.v file as toplevel

07:34 <krickit> i have to error up

07:35 <_florent_> ok

07:35 <_florent_> last time i tested it was building correctly, i would need to try again

07:36 <krickit> to add pico32

07:36 <_florent_> have you try installing the open source toolchain (Yosys/Trellis/NextPnr)?

07:36 <krickit> nope, i have to use diamond

07:38 <_florent_> ok, just for info about the open source toolchains, you can get prebuilt binaries from https://github.com/open-tool-forge/fpga-toolchain/tags

07:38 <_florent_> what command line are you using? because i don't understand why you are mentioning pico32 (the default CPU is vexriscv)

07:40 <daveshah> Any reason why you are using WSL and not native Windows Diamond?

07:40 <krickit> ./versa_ecp5.py --device=LFE5UM --toolchain=diamond --cpu-type=picorv32 --sys-clk-freq=100e6

07:41 <krickit> i'm using WSL only for linux command operation

07:41 <krickit> Diamond is on windows

07:41 <daveshah> Hmm, I wonder if that arrangement is causing problems

07:42 <_florent_> that's indeed possible

07:43 <daveshah> I have certainly seen WSL fail in strange ways before

07:44 <krickit> ok,

08:10 <st-gourichon-fid> keesj, _florent_ thank you for your feedback. I make a PR.

08:14 <keesj> morning

08:14 <st-gourichon-fid> morning everyone

08:18 <keesj> I was trying to setup quickfeather last week and I think it have been setup to allow cross os installation (include WSL) but the whole conda thing and download of binaries "to make it easy" is not very userfriendly to me. I got the same kind of problems with docker "just run this command and everything will work" causes a lack of documentation and creates a layer of confusion that only really help noobs (and

08:18 <keesj> makes it very hard to step into open source)

08:19 <keesj> but .. WSL has been pretty good to me (makes me feel at home/productive when I need to use windows)

09:14 <st-gourichon-fid> PR done: https://github.com/enjoy-digital/litex/pull/678

09:17 <st-gourichon-fid> Hmm, wasn't there a bot that posted titles of URLs appearing in the channel? Anyway: "DFUProg now checks and propagate return codes of called executables... #678"

09:46 <acathla> versa_ecp5 does not build because: "ERROR: Net 'init_rst' is multiply driven by cell ports FD1S3BX_3.Q and FD1S3BX_5.Q"

09:49 <_florent_> st-gourichon-fid: thanks for the PR, we are generally trying to raise the error when it happens, i'll have a closer look later

09:51 <_florent_> acathla: it's related to the changes in ECP5PLL that is now handling rst internally, i think i fixed it but possible the target it not up to date in litex

09:51 <st-gourichon-fid> _florent_, yes, I have seen more areas where processes are spawn without checking. "Small steps"...

10:01 <_florent_> acathla: the versa_ecp5 target was not up to date in litex, i just updated it

11:19 <dkozel> futarisIRCcloud: Thanks for that! I'm very interested in how miek's work continues.

11:52 <acathla> _florent_, it's works! thank you

15:49 <mithro> OpenRAM on SKY130 talk from Matt as part of FOSSi Foundation DialUp talk series is starting in 10 minutes -- https://youtu.be/9Lw83kFtnc4

17:40 <acathla> it works* ( hours later...)