_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<a314> is there some straightforward way to do verilog builds from LiteX?
<a314> My specific environment requires me to generate verilog and then feed it into a specific build system, instead of using LiteX's platforms
<a314> but it seems that the SoC classes all require a Platform
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<a314> Running into a "ERROR: Conflicting init values for signal 1'0 (\basesoc_csr_bankarray_interface2_bank_bus_dat_r [4] = 1'x != 1'0)." when trying to yosys-synthesize a simple LiteX design exported as verilog
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<daveshah> Is your Yosys up to date? I think a similar bug was fixed a few months ago
<daveshah> This definitely looks like a Yosys issue rather than a LiteX one either way
<a314> 09ecb9b2
<a314> so early july
<a314> not sure if that's new enoguh
<daveshah> I'd try updating that before anything else, just in case
<_florent_> a314: you can export yo verilog by creating a generator, similar to: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py
<a314> daveshah: yeep that fixed it, thanks
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<a314> is there any reason why a UARTWishboneBridge would be failing to write but always succeeding on reads?
<a314> it takes 3-5 write-sends with wishbone-tool in order to get the value to change
<a314> tried with both GPIOOut and SRAM
<a314> but reads work perfectly, tried it with GPIOIn and updates effectively immediately
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