02:37 <futarisIRCcloud> dkozel: https://twitter.com/assortedhackery/status/1317849554629296129

12:59 <krickit> hi everybody

12:59 <daveshah> hi!

12:59 <krickit> hi everybodhi daveshah

13:00 <krickit> i have a problem with liteX

13:00 <krickit> i used a folder gateware in my fpga tool

13:01 <krickit> but when i try to syntetize there are a lot of errors

13:01 <daveshah> What errors?

13:01 <krickit> i think that there isn't a pico's module

13:01 <daveshah> Yes, you will need to add that file too

13:02 <daveshah> have a look at the tcl/ys/whatever file litex generates in the gateware folder for the path for that

13:02 <krickit> ok, thanks i try

13:02 <krickit> if i have problems can i ask you?

13:17 <st-gourichon-fid> Hi everyone. Class DFUProg does not provide any hint when things go wrong: https://github.com/enjoy-digital/litex/blob/master/litex/build/dfu.py#L14

13:18 <st-gourichon-fid> Could be return code or exception. Dunno what is the stance here regarding pythonicity of code. Anyway I coded near-trivial changes to propagate return code from cp/dfu-suffix/dfu-util to caller, which allows caller scripts to at least exit with a non-zero return code when things went wrong.

13:19 <st-gourichon-fid> TL;DR: Before change, failure goes unnoticed in build (including CI build etc), after change failure gets noticed. Can do quick PR.

14:10 <krickit> Running DRC...

15:03 <krickit> Running DRC...

15:16 <krickit> probably i didn't understand steps:

15:17 <krickit> i follow guide here https://github.com/enjoy-digital/litex

15:18 <krickit> i open targets folder and i run the python for my board

15:18 <krickit> now I have the gateware folder and i add picorv file inside

15:19 <krickit> I create a project in my fpga tool with all files and i run synthesis

15:20 <krickit> ?

16:09 <keesj> what is the question?

20:12 <keesj> st-gourichon-fid: nice