_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<krickit> hi everybody
<daveshah> hi!
<krickit> hi everybodhi daveshah
<krickit> i have a problem with liteX
<krickit> i used a folder gateware in my fpga tool
<krickit> but when i try to syntetize there are a lot of errors
<daveshah> What errors?
<krickit> i think that there isn't a pico's module
<daveshah> Yes, you will need to add that file too
<daveshah> have a look at the tcl/ys/whatever file litex generates in the gateware folder for the path for that
<krickit> ok, thanks i try
<krickit> if i have problems can i ask you?
<st-gourichon-fid> Hi everyone. Class DFUProg does not provide any hint when things go wrong: https://github.com/enjoy-digital/litex/blob/master/litex/build/dfu.py#L14
<st-gourichon-fid> Could be return code or exception. Dunno what is the stance here regarding pythonicity of code. Anyway I coded near-trivial changes to propagate return code from cp/dfu-suffix/dfu-util to caller, which allows caller scripts to at least exit with a non-zero return code when things went wrong.
<st-gourichon-fid> TL;DR: Before change, failure goes unnoticed in build (including CI build etc), after change failure gets noticed. Can do quick PR.
<krickit> Running DRC...
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<krickit> Running DRC...
<krickit> probably i didn't understand steps:
<krickit> i follow guide here https://github.com/enjoy-digital/litex
<krickit> i open targets folder and i run the python for my board
<krickit> now I have the gateware folder and i add picorv file inside
<krickit> I create a project in my fpga tool with all files and i run synthesis
<krickit> ?
<keesj> what is the question?
<keesj> st-gourichon-fid: nice
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