_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<lkcl> futarisIRCcloud: hoo boy, 900k LUTs and 8GB of RAM, dang!
<daveshah> These are pretty cool too
<tpb> Title: SQRL BCU-1525 / VCU-1525 FPGA | eBay (at www.ebay.com)
<daveshah> 2.5M logic cells, 4 DDR4 DIMMs, 2xQSFP28
<daveshah> not HBM like the fk33 tho
<lkcl> there's a bug in SDRIO
<lkcl> - return InferedSDRIO(dr.i, dr.o, dr.clk, dr.clk_domain)
<lkcl> + return InferedSDRIO(dr.i, dr.o, dr.clk) # dr.clk_domain)
<lkcl> litex/build/io.py
<lkcl> anyone know the "correct" fix here?
<tpb> Title: build/io: fix InferedSDRIO (thanks @mtdudek). · enjoy-digital/litex@9950e75 · GitHub (at github.com)
<dkozel> futarisIRCcloud: Thanks! With GRCon done now I'm definitely getting back to gr-litex
<dkozel> Several folks have bought CEL215 boards now so it'll be good to have a group working on it
<futarisIRCcloud> I have two CLE-215+ here. And a HackRF.
<dkozel> futarisIRCcloud: nice! I'm at the point where i need to figure out how to setup DMA from the litePCIe interface to a core on the bus and then back to PCIe
<dkozel> I have the GNU Radio side working where I can stream to/from the PCIe in loopback
<dkozel> It's been sitting undocumented for a while. Need to get it posted
<dkozel> probably there's some catching up with LiteX and litePCIe to do
<lkcl> PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND
<lkcl> 365243 lkcl 20 0 11.073g 0.010t 14216 R 100.0 17.0 26:21.76 yosys
<lkcl> yee-hee-yowwwser!
<lkcl> that's compiling a litex-generated pinout for an ASIC
<daveshah> The memories will be being bitblasted
<lkcl> daveshah: ahh
<lkcl> it may be interfering with yosys-abc (which is segfaulting)
<daveshah> The solution will either to have LiteX use memory compiler primitives instead; or remove all calls to memory_map in your Yosys script so you are left with $mem cells (less ideal but maybe you can use memory_bram to map them to your ASIC primitives)
<lkcl> daveshah: makes some sense, i know that staf (chips4makers) and jean-paul (coriolis2) will understand that
<lkcl> daveshah: you mean stuff like this:
<lkcl> Consolidated identical input bits for $mux cell $memory\mem$rdmux[0][9][93]$90622:
<lkcl> etc. etc. ?
<lkcl> if that happens, equals Bad(tm)?
<daveshah> If the memory is large enough, yes
<daveshah> That's some attempt to optimise the memory after it has been bitblasted by the looks of things
<lkcl> it's a... 64k ROM
<lkcl> 1 of them is a 64k ROM (litex BIOS)
<lkcl> the other's the SRAM which i reduced to 8k
<lkcl> i don't actually want a ROM in the ASIC, not for a test chip, that is.
<lkcl> will be using JTAG to write to SRAM
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<lkcl> libresoc 180nm "peripherals" created by litex, plus the core, compiled / routed under coriolis2. yay!