08:27 <pepijndevos> Suppose I want to add Gowin support to LiteX...

08:29 <pepijndevos> Looking around a bit at the Latice stuff...

08:31 <pepijndevos> Can a platform for example synth with yosys and use vendor PnR? Seems that with Lattice it's either Diamond or Trellis not a mix, right?

09:06 <zyp> I don't see why not as long as it's added as a supported combination

09:13 <pepijndevos> I guess

09:35 <pepijndevos> I'm kinda unsure how the constraint stuff works, but the rest seems... doable

09:43 <_florent_> pepijndevos: on Lattice FPGA we are indeed not mixing between Vendor/Open source toolchains. You choose either Diamond or Yosys/IceStorm/Trellis, but on Xilinx FPGAs it's possible to do the synthesis with Yosys and P&R with Vivado.

09:45 <_florent_> pepijndevos: which Gowin board are you planning to support first? I could order one if that can help

11:40 <pepijndevos> _florent_, https://shop.trenz-electronic.de/en/TEC0117-01-FPGA-Module-with-GOWIN-LittleBee-and-8-MByte-internal-SDRAM?c=508

11:47 <pepijndevos> Time to copy stuff from Xilinx then I guess

11:47 <pepijndevos> I hope I can use some of the code in Apicula to drive the vendor tools...

12:00 <pepijndevos> Do you actually have a CI machine with a dozen FPGA boards connected? Would be funny...

12:02 <pepijndevos> Do I actually need to implement all these special overrides, or just add them later as needed?

12:13 <pepijndevos> Hm, it seems in the case of Xilinx there is still one toolchain, but vivado can use yosys.

12:14 <pepijndevos> Is the toolchain parameter to the platform an implicit contract, or can I make my platform take a synth and a pnr toolchain seperately?

12:19 <pepijndevos> What should I put in the copyright parts? Just me, just _florent_ , me and _florent_ ?

12:31 <pepijndevos> What is build supposed to return?

16:34 <pepijndevos> What's an easy way to test my platform without building a huge SoC?

17:23 <_florent_> pepijndevos: thanks, i'll order the trenz board. I ordered some parts recently to build a CI machine with several boards connected to it but haven't had time yet to build it.

17:24 <_florent_> if you want to start with a simple SoC, you can use https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/simple.py

17:24 <tpb> Title: litex/simple.py at master · enjoy-digital/litex · GitHub (at github.com)

17:24 <pepijndevos> thanks

17:24 <_florent_> that's basically a SoC with CPU + ROM + SRAM + UART that should work on all devices

17:24 <pepijndevos> I think I'm getting there... but Gowin keeps changing their TCL API so everything is different with the newest version

17:25 <_florent_> this just requires a clock input + UART pins

17:25 <_florent_> and should not require the special overrides

17:25 <pepijndevos> I now took the first example for the tutorial which is even more basic hehe, but yea once I have anything working *at all* that one will be next.

17:28 <pepijndevos> But yea, basically they completely change their api on patch version. Between 1.9.3 and 1.9.6 it just completely broke all my existing code, so can't promise anything I'm writing now will work in 1.9.7 :(((

17:31 <_florent_> for the copyrights, feel free to only add your name, most of the work here is not really what is reused from other toolchain support but more figuring out how to use/drive the toolchain, so the work you are currently doing.

17:32 <pepijndevos> alright