_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<_florent_> somlo: nice, with all the efforts on the gateware/driver, let's hope we'll have something a bit faster than the spi-mode implementation :)
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<pepijndevos> I can't seem to get any code running on my SoC, maybe because it runs out of RAM... time to fix that I guess...
<lkcl> what's the devboard you're using there?
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<pepijndevos> lkcl, Trenz TEC0117 or something
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<lkcl> nice. pity the gowin FPGAs don't go above 55k LUTs
<pepijndevos> I read some vague news about a bigger device but no real info anywhere.
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<pepijndevos> blegh... if I remove sram and try to use spirom only it complains that it needs sram linker region
<loxodes>
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<leons> wohoo, my OS port to LiteX is starting to get usable. thanks for all the awesome work! :)
<leons> As a next step (to better understand nMigen & LiteX) I'd like to drive a small SPI-based sensor in HW. I've looked in the litespi repository for quite some time, but don't really know how to get started with a core using a SPI master
<leons> Is there any example of something similar? I.e. instantiating a SPI Master which is not used for flash? I'd be grateful for any hints where to look
<_florent_> leons: great, for SPIMaster you can also use: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi.py#L16
<tpb> Title: litex/spi.py at master · enjoy-digital/litex · GitHub (at github.com)
<_florent_> that's what we are using for SD card in SPI mode for example: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1377-L1385
<tpb> Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com)
<tpb> Title: litex/spisdcard.c at master · enjoy-digital/litex · GitHub (at github.com)
<leons> that looks much more comprehensible to me! I didn't even look in the main repo once I found litespi :)
<mithro> litespi should maybe have a bigger WIP thingy on it
<mithro> _florent_: BTW We are getting very close to being able to run LiteX designs with the symbiflow toolchain without any modificatoins
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<kbeckmann> hi, it seems that https://github.com/enjoy-digital/litex/commit/4f766560180bc4869186de40b2d816eee0ae6a16 introduced a regression where it's not possible to build projects using sdram anymore. it can't link: "undefined reference to `sdram_leveling'". Tried to build ulx3s with default parameters.
<tpb> Title: software/liblitedram: simplify vtc/hardware/software controls. · enjoy-digital/litex@4f76656 · GitHub (at github.com)
<kbeckmann> looking at it quickly I guess we should surround the leveling call with #if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) || defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
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<kbeckmann> made a pr, but I am not really sure what I'm doing here so please reject or solve it in another way if that is more appropriate :)
<zyp> sdram_leveling() is also called from sdram_cal_handler(), but I guess the defines there are already taking care of that?
<zyp> did you check that it builds properly with your fix?
<kbeckmann> it builds for ulx3s and i booted the bios, i had not tested anything more.
<kbeckmann> have*
<kbeckmann> the code you mentioned zyp is not being built for ulx3s, however i am not too sure about the defines here. so there could be some situation where it will not build since the ifdefs are different.
<zyp> I'm not sure about it either, just spotted that there were two calls to sdram_leveling() in the first commit you linked
<kbeckmann> thanks. yeah i am not very confident in this change but figured it's nicer to make a pr than just complain :)
<zyp> absolutely
<zyp> a PR is a proposal, up for review
<zyp> doesn't need to be perfect at the first attempt :)
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