_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<lkcl> does anyone know of examples where litex peripherals have been done as verilog?
<lkcl> e.g. some opencores stuff - uart, i2c, or other?
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<_florent_> lkcl: you can look here for I2C, PWM, UART, etc.... https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py
<tpb> Title: litex/litex_gen.py at master · enjoy-digital/litex · GitHub (at github.com)
<_florent_> ah, but not sure i understood your question correctly
<_florent_> if that's the other way (integrating verilog code), i can try to find code
<_florent_> you can find here an example of I2C core integrated with LiteX: https://github.com/betrusted-io/gateware/blob/master/gateware/i2c/core.py
<tpb> Title: gateware/core.py at master · betrusted-io/gateware · GitHub (at github.com)
<lkcl> i need to be able to pull in e.g. opencores 16550 uart written in verilog
<lkcl> and present it as a peripheral that can be added to litex
<lkcl> and richard herveille's opencores RGB/TTL
<lkcl> and i *think*.... that bunnie huang code is exactly it.
<lkcl> eyy it's even richard herveille's i2c opencores rtl :)
<lkcl> _florent_, thank you.
<lkcl> _florent_: for ASICs, all tristate signals must not be handled by litex, the "_i", "_o", "_oe" signals must be brought out (individually, explicitly) and wired up directly to IO pad cells.
<lkcl> i have easily been able to do an SDRAMPHY replacement class that handles this:
<lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=9c7547f7078522cedccb5cc38f2beed6e58b7f6b;hb=HEAD#l121
<tpb> Title: git.libre-soc.org Git - soc.git/blob - src/soc/litex/florent/ls180soc.py (at git.libre-soc.org)
<lkcl> sorry, line 168
<lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/litex/florent/ls180soc.py;h=9c7547f7078522cedccb5cc38f2beed6e58b7f6b;hb=HEAD#l168
<tpb> Title: git.libre-soc.org Git - soc.git/blob - src/soc/litex/florent/ls180soc.py (at git.libre-soc.org)
<lkcl> however, GPIOTristate had to be completely replaced because it does not take a "gpio_phy_cls" parameter
<lkcl> SDCard likewise because that does not take a "sdcard_phy_cls" parameter i had to duplicate very large sections of the code
<lkcl> and SDRPad
<lkcl> spi is good (no Tristate)
<lkcl> uart is good (except i had to duplicate the code in add_uart because, again, you can't pass in your own PHY class)
<lkcl> PWM is good
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