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<
lkcl >
does anyone know of examples where litex peripherals have been done as verilog?
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lkcl >
e.g. some opencores stuff - uart, i2c, or other?
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tpb >
Title: litex/litex_gen.py at master · enjoy-digital/litex · GitHub (at github.com)
19:27
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_florent_ >
ah, but not sure i understood your question correctly
19:28
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_florent_ >
if that's the other way (integrating verilog code), i can try to find code
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tpb >
Title: gateware/core.py at master · betrusted-io/gateware · GitHub (at github.com)
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lkcl >
i need to be able to pull in e.g. opencores 16550 uart written in verilog
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lkcl >
and present it as a peripheral that can be added to litex
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lkcl >
and richard herveille's opencores RGB/TTL
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lkcl >
and i *think*.... that bunnie huang code is exactly it.
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lkcl >
eyy it's even richard herveille's i2c opencores rtl :)
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lkcl >
_florent_, thank you.
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lkcl >
_florent_: for ASICs, all tristate signals must not be handled by litex, the "_i", "_o", "_oe" signals must be brought out (individually, explicitly) and wired up directly to IO pad cells.
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lkcl >
i have easily been able to do an SDRAMPHY replacement class that handles this:
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tpb >
Title: git.libre-soc.org Git - soc.git/blob - src/soc/litex/florent/ls180soc.py (at git.libre-soc.org)
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lkcl >
sorry, line 168
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tpb >
Title: git.libre-soc.org Git - soc.git/blob - src/soc/litex/florent/ls180soc.py (at git.libre-soc.org)
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lkcl >
however, GPIOTristate had to be completely replaced because it does not take a "gpio_phy_cls" parameter
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lkcl >
SDCard likewise because that does not take a "sdcard_phy_cls" parameter i had to duplicate very large sections of the code
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lkcl >
spi is good (no Tristate)
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lkcl >
uart is good (except i had to duplicate the code in add_uart because, again, you can't pass in your own PHY class)
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