<dudeski>
I'm new to the Litex / Migen scene. Can anyone tell me how i could generate Verilog for an individual component such as the LiteDram for the Arty, so that i could test it with an existing design?
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<keesj>
i likt eh connectors (e.g. not the pmod stuff but something with more connections)
<SpaceCoaster_>
Ranzbak: the upduino_v1.py platform file has the sb_hfosc instance integrated into the platform.request structure. The v1 doesn’t have an external oscillator so the internal one is used. It is in LiteX-boards.
<lkcl__>
_florent_, daveshah: thank you for all your help and patience
<keesj>
power9 ? (The revolutionary IBM POWER9 processor chip) ?
<keesj>
https://twitter.com/raptorcompsys/status/1225186761208401920 Check out #Symbiflow...Lattice ECP5 tooling from synthesis to programming the FPGA is 100% open source, supports timing constraints, runs on POWER, and generally does a very good job!
<lkcl__>
keesj: yes. a POWER9 compliant core.
<lkcl__>
that's raptor running microwatt which is POWER9. this is libresoc which is also POWER9
<sorear>
itym Power Architecture V3.00
<sorear>
for someone very concerned about risc-v trademarks you don't seem to use IBM's carefully
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<_florent_>
lkcl__: nice you got it working
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<lkcl__>
sorear: the EULA by IBM says that you can't use the words "POWER9 compliant", and also that open source FPGA implementations have an exemption from needing "Compliance testing" prior to release
<lkcl__>
someone pointed out that an earlier version of the EULA completely prohibited open source FPGA implementations from being made public until they were properly and fully POWER9 compliant... against a Conformance Test Suite that hasn't even been written yet :)