17:24 <david-sawatzke[m> Hi, I'm trying to use the colorlight 5a-75b, but when trying to build the target example with `./litex_boards/targets/colorlight_5a_75x.py --build`, it errors out with `4.39. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

17:24 <david-sawatzke[m> ERROR: Conflicting init values for signal 1'0 (\builder_basesoc_wishbone_dat_r [8] = 1'0 != 1'x).`

17:24 <david-sawatzke[m> Does anyone know what's going wrong?

17:25 <daveshah> Is your Yosys up to date?

17:27 <david-sawatzke[m> Should be, it's the most recent one in nexpkgs: `$ yosys --version

17:27 <david-sawatzke[m> Yosys 0.9+2406 (git sha1 000fd08198, g++ 9.3.0 -fPIC -Os)`

17:28 <david-sawatzke[m> * Should be, it's the most recent one in nixpkgs: `$ yosys --version Yosys 0.9+2406 (git sha1 000fd08198, g++ 9.3.0 -fPIC -Os)`

17:30 <daveshah> That's about two months old

17:30 <daveshah> I think there might have been a fix for the issue after that

17:31 <daveshah> latest should be 0.9+3565

18:01 <david-sawatzke[m> Thanks, ran into some other issues along the way, so can't test if it's fixed by updating

20:27 <lkcl> XICS interrupt handler (equivalent to RISC-V PLIC) in LibreSOC is functional, under litex sim.py