_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<benh> pdp7: I'm of 2 minds about the regmap ... that said, there are ways to improve the direct map case
<benh> by special-casing it in the accessors themselves
<benh> if it becomes a real issue
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<SpaceCoaster> I am having a problem using vexriscv minimal on ECP5 AND ICE40 UP5K. It used to work fine but now I don’t get a prompt from the bios. The ECP5 doesn’t matter so much but anything larger than minimal does fit in the up5k
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<SpaceCoaster> Ok nix that, it works on the ECP5 now.
<SpaceCoaster> I am updating the upduino board files to support the v2 and the internal low speed oscillator. The icebreaker platform file has interesting support for flash and psram
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