_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<futarisIRCcloud> https://twitter.com/ConnorKrukosky is his Twitter
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<feldim2425> When creating a new SoC is it better to extend LiteXSoC or SoCCore? soc_core.py has a disclaimer that it is for retro-combatibility however LiteXSoC seems to be incompatible with the Builder.
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<lkcl_> feldim2425: florent helped us create a sim.py and versa_ecp5.py for libre-soc, and the versa_ecp5.py is based on litex/boards/targets/versa_ecp5.py
<lkcl_> that module creates something called BaseSoC which is derived from SoCCore
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<feldim2425> The comment in the soc_core.py confused me a bit. The wording suggests that SoCCore is there just for retro compatibility and shouldn't be used however the BaseSoC's still use it and the Builder seems to throw errors about missing attributes if I don't extend from SoCCore or a BaseSoC. So I think I'll stay with SoCCore.
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<[Matt]> Evening all- has anyone used ac701 in recent memory? I'm trying to get litex-boards' targets/ac701.py running and it reliably fails memtest (on both of the AC701s I have). I noticed other boards w/ the same DDR3 SODIMM config A7DDRPHY with cmd_latency=1; adding this reduces the number of failures but still ~50% N/M errors. Anyone have any ideas?
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