09:07 <pepijndevos> When I want to add a peripheral to my SoC, do I just copy the target and edit it?

09:34 <pepijndevos> The ULX3S platform file covers far from all the available pins. Should I submit a PR for adding more of https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf or just add my own stuff locally?

09:34 <tpb> Title: ulx3s/ulx3s_v20.lpf at master · emard/ulx3s · GitHub (at github.com)

09:56 <_florent_> pepijndevos: you can import the litex target in your design and create a new SoC based on BaseSoC, for the IOs, if it's not too specific to a project, we can create a PR to add them, otherwise ou can define them in your design and use Platform.add_extension

09:57 <pepijndevos> ok

09:58 <_florent_> mithro: nice, would you mind asking someone from the Symbiflow team to create a PR to update the Arty target if some of the workarounds are no longer needed?

10:02 <pepijndevos> Trying to understand if I can make a SPI master core without a MISO? I'm looking at https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi.py and it's not obvious to me how the pads variable relates to the defined signals.

10:02 <tpb> Title: litex/spi.py at master · enjoy-digital/litex · GitHub (at github.com)

10:10 <pepijndevos> pads.miso = Signal() seems to make it happy... for now

17:50 <mithro> _florent_: Will do

19:42 <pepijndevos> How do I debug my binary seemingly not running at all depending on trivial changes?

20:18 <daveshah> If you are using nextpnr, trying different seeds with the same json is a good way to see if the issue is related to P&R

20:18 <daveshah> as opposed to something breaking in the netlist or during synthesis