_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<futarisIRCcloud> Anyone want to make some LiteX stickers?
<tpb> Title: 8 € pour 50 | Sticker Mule France (at www.stickermule.com)
<tpb> Title: $12.80 for 50 | Sticker Mule Australia (at www.stickermule.com)
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<_florent_> lkcl: hi, have you been able to do tests with the simplified targets i provided you? The aim was first to get basic design working without DRAM, because i was expecting it to cause troubles at the frequencies that can be achieved with the current version of your CPU.
<_florent_> if you want to remove the DRAM from the design, you can add --integrated-main-ram-size=0x1000 to the command line
<_florent_> i would first recommend getting this working in a first time, for the DRAM, it's currently synchronous to the CPU, so this will indeed cause troubles with the frequencies you are targeting, we could have a mechanism to decouple that, but it's not currently in place since hasn't been useful in the past
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<lkcl> _florent_, i am using them, yes.
<lkcl> yes we really need the DRAM clock decoupled. there is a Broadcast Bus with over 20x 64-bit INT registers accessing the Regfile Read port
<lkcl> the MUX tree that is created is so large that it results in massive routing and there's unlikely to be any way that i can get the speed even above 48mhz as a result
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<lkcl> _florent_: yep, setting 16mhz and disabling DRAM works great.
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<tpb> Title: Custom AXI IP for acceleration. controlpaths. (at www.controlpaths.com)
<awygle> there's no bench for ecp5 in litedram's repo, do we have an idea of about how fast a memory it can handle on those parts?
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