04:52 <davidcorrigan714> avg alan?

04:52 <avg> Yes!

04:53 <davidcorrigan714> Cool, was about to leave some notes about trying to connect to untangle some commits. Not sure you if it's alerted you yet for some of the comments I had left on things

04:56 <avg> ah yes - the list of primitives is confusing

04:57 <avg> The SP512K primitive corresponds to the architecture of the LRAMs

04:57 <avg> and then SP16K matches the Crosslink EBRAMs

04:58 <avg> The reference guide is light on helpful detail

04:59 <avg> SP256K is the iCE40 SPRAM

05:03 <davidcorrigan714> ok, found the section of the datasheet that kind of spells that out more. So you did the SP512K which would do LRAM and I went for the SP16K which is block ram. Not sure how the distributed RAM bits work or if those mostly get used in other things. Seems like just names need sorting then since both types are useful.

05:04 <avg> If i'm reading it correctly, distributed RAM uses FFs, so probably not generally useful connected to Wishbone

05:05 <avg> Agree both BRAM and LRAM ram is useful - on the NX/40, I'm planning to use 256kB BRAM + 256kB LRAM

05:10 <avg> fwiw, Radiant is telling me that the 125MHz clock can't be used directly - it looks like it is intended only for use with the SERDES block

05:10 <avg> So, working on getting the 12MHz clock going

05:12 <davidcorrigan714> I've got the 450 Mhz one setup and you can divide it down. Pushed those a few minutes ago

05:12 <avg> Ah, the internal oscillator? nice

05:13 <davidcorrigan714> yeah, the accuracy is something like 15% but it works. I accidentally had it at 90 Mhz the first go and it actually worked but I set the default to 75 Mhz.

05:14 <davidcorrigan714> The OSCA block has the 450 Mhz core with 2 divided outputs, then a slower clock as well, forget the exact speed, but I haven't quite figured out how to nicely expose that slower one with the way the faster two output are structured in the code.

05:15 <davidcorrigan714> I've got to run for the evening, but I'm curious about the tooling naming difference. May just have to put an OS check for the name if they're really separate on the two platforms.

05:43 <daveshah> avg: is there any need to use RAM primitives?

05:43 <daveshah> A big enough main ram in LiteX should hopefully end up inferred to LRAM anyway

05:46 <avg> @daveshah I will check that out in the near future

05:47 <avg> Is there an example of another FPGA with largish special purpose rams that are inferred? I"m only familiar with iCE40 and Artix7

05:48 <daveshah> Yes, UltraScale+ URAMs are inferred

05:48 <avg> ty!

06:29 <avg> @daveshah Radiant seems to be inferring BRAMs instead of LRAMs.

06:30 <daveshah> Ah, that's a shame