12:03 <ninou> hi

13:30 <keesj> hi

17:01 <tmbinc> I apologize if this is common knowledge - does litex support building PL for a Zynq system, i.e. interfacing to the PS AXI ports?

17:02 <pdp7> benh: one of the interesting bits of discussion is that Jonathan Cameron (iio maintainer) felt that regmap was definitely the way to go and that a few extra function calls to access CSRs should not be a problem.

17:02 <tmbinc> I'm tempted to continue this "open source bitstream for siglent scopes" project but I'm fed up with Vivado's block design, and part of the logic is already written with migen anyway (ADC interface etc.), which is/was an integration painpoint

17:02 <pdp7> It is unfortunate that it is such a bad time for Australia

17:03 <pdp7> benh: it was great when you got involved back in June

18:48 <_florent_> tmbinc: hi, yes it's possible to create a SoC on Zynq with LiteX and interface it with the PS, you can look at:

18:48 <_florent_> https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu/zynq7000

18:48 <tpb> Title: litex/litex/soc/cores/cpu/zynq7000 at master · enjoy-digital/litex · GitHub (at github.com)

18:49 <_florent_> https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/zybo_z7.py

18:49 <tpb> Title: litex-boards/zybo_z7.py at master · litex-hub/litex-boards · GitHub (at github.com)

18:51 <tmbinc> oh very nice! Is there a Wishbone2AXI as well so I can drive the HP ports from wishbone logic?

18:52 <tmbinc> i.e. the PL -> PS ports

19:01 <_florent_> i was also interested by 360nosc0pe project, but haven't really explored it for the same reasons (Vivado's block design)

19:02 <_florent_> we have adapters for all the AXI interfaces yes: GP/HP in both directions

19:03 <_florent_> if you want to play with this, i also have the scope and could try to help