_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<_florent_> somlo: thanks for looking at this, i merged you PR and fix the tests to specify wishbone address width when required
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<pepijndevos> What do the EV_* registers on UART do? Trying to implement a flush operation.
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<somlo> _florent_: thanks -- being relatively new to python, I got blindsided by the default parameter value thing, and the overriding theeof :)
<_florent_> pepijndevos: these registers are related to the interrupts
<pepijndevos> So... is there a way to tell if the txqueue is *empty*?
<_florent_> pepijndevos: looking at https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/libbase/uart.c#L28-L52 should give you some insights
<tpb> Title: litex/uart.c at master · enjoy-digital/litex · GitHub (at github.com)
<pepijndevos> looking...
<_florent_> in fact no, you can only know if TX is full, not empty, but that's something we could add if you really need it
<pepijndevos> https://docs.rs/embedded-hal/0.2.4/embedded_hal/serial/trait.Write.html has a flush method, which is basically waiting for tx to be empty, right?
<tpb> Title: embedded_hal::serial::Write - Rustembedded-hal 0.2.4 - Docs.rs (at docs.rs)
<tpb> Title: cores/uart: add txempty/rxfull CSRs. · enjoy-digital/litex@e0f131a · GitHub (at github.com)
<pepijndevos> _florent_, haha amazing thank you
<somlo> _florent_: I got LiteSDCard working fine with rocket on the trellisboard (built-in slot, no pmod) by further lowering SDCARD_CLK_FREQ to 15MHz (admittedly, sys_clk on the trellisboard was 60MHz, rather than 75 like on nexys4ddr)
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<_florent_> somlo: the throttling mechanism should be in place and seems to behave correctly on hardware, could you do a test on your side?
<somlo> _florent_: will start a build right away, thanks!
<somlo> _florent_: do we also want to put the sdcard frequency back up to 50MHz?
<somlo> with the throttling in place, I mean?
<_florent_> somlo: ah yes, i did that locally but forgot to push
<_florent_> can you try at 50MHzN
<_florent_> ?
<somlo> will do
<_florent_> or at least with a speed that was not working correctly before throttling
<somlo> building (nexys4ddr and trellisboard) with 50...
<tpb> Title: interconnect/wishbone: increase WB address width to 31 · enjoy-digital/litex@70eae5c · GitHub (at github.com)
<somlo> I'd rather not add parameters to each cpu's core.py __init__() method -- it'd be nicer if we could detect the extra address width closer to where the interface is created...
<_florent_> yes sure, i'm looking at this, i want to revert the default adr_width to 30 and just specify when needed for the dma
<somlo> basically, the add_slave call here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L848 has the authoritative width information
<tpb> Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com)
<somlo> and it passes it on to the call to add_adapter here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L377
<tpb> Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com)
<somlo> so if we passed the width through that chain and made it available here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L291 maybe we could avoid touching the Interface() defaults in wishbone.py altogether
<tpb> Title: litex/soc.py at master · enjoy-digital/litex · GitHub (at github.com)
<somlo> I want to try that as soon as the sdcard throttling builds are done, see if it's enough to get rocket working with reverted wishbone width changes
<_florent_> somlo: i reverted the default adr_width to 30 and added this: https://github.com/enjoy-digital/litex/commit/b1008b01642c12c8f9d2253372f027ebd659b9e5
<tpb> Title: integration/soc: add expection on decoder when full address space is … · enjoy-digital/litex@b1008b0 · GitHub (at github.com)
<_florent_> i haven't tested on hardware, but i think it should work
<_florent_> could you try this with Rocket/DMA?
<_florent_> somlo: possible this will not be enough, if not i'll have a look tomorrow
<somlo> _florent_: I'll try it on hardware as soon as the other (throttling) build (which is still in progress) completes :)
<somlo> b1008b01 looks a bit cryptic, but will force me to take another tour of the sources to understand it, which is not altogether a bad thing :)
<somlo> _florent_: got a file read error about 1/3 the way through loading boot.bin from sdcard on the nexys4ddr
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<pepijndevos> disasm[m], thanks for all the help along the way, I wrote a blog post about my project: http://pepijndevos.nl/2020/08/04/a-rust-hal-for-your-litex-fpga-soc.html
<tpb> Title: A Rust HAL for your LiteX FPGA SoC - Wishful Coding (at pepijndevos.nl)
<pepijndevos> and also thanks to _florent_ :)))
<pepijndevos> esden you may also find it interesting, I based it loosely on your icebreaker examples, but focused more on implementing HAL traits so you can reuse libraries
<disasm[m]> I don't really like extensive use of macros in hals for reasons, but this is quite a good experiment :)
<levi> @pepijndevos Nice writeup! I will be following along that path at some point, as I've got a pile of Spartan 6 boards with gigabit ethernet that I want to do RiscV+Rust on.
<somlo> _florent_: back down at 25MHz, and with b1008b01, vivado is happy to compile a nexys4ddr bitstream (the reverted wb addr. width enlargement was to stop vivado from erroring out)
<somlo> and the bitstream works OK (at 25MHz liteSDcard clock)
<somlo> so it's just the sdcard clock vs. throttling that's still an issue...
<_florent_> somlo: ok, that's already good if the DMA works
<_florent_> somlo: i'll see if i can have another look tomorrow at the throttling mechanism, but otherwise we'll keep 25MHz for now, it does not make that much difference with the size of the binaries we are currently loading
<_florent_> pepijndevos: nice, thanks for sharing
<pepijndevos> disasm[m], all ears to ways to avoid extensive macros in HALs... after some good sleep ;)
<pepijndevos> Even the STM HAL is basically one giant macro and that's supposed to be a reference
<disasm[m]> I'll try to make a PR, but in general we need a better approach for other parts too :)
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<disasm[m]> pepijndevos: where can I get the `litex-pac` lib?
<disasm[m]> Nevermind, I made my own
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