00:21 <futarisIRCcloud> Great discussion on how to renumerate LiteX SoC over PCIe. Android USB Accessory is another example of how one protocol is enumerating over another. I guess Linux USB over IP is another.

02:27 <atommann> Good morning.

10:24 <TMM> _florent_: well, I bought an Arty A7-35T! :D

10:54 <acathla> TMM, congratulations! But that was the easy part :)

11:30 <trabucayre> I regret lack of USB port on this board

11:50 <zyp> _florent_, I've been going through litepcie to figure out how stuff fits together, got a couple of questions if you don't mind

11:51 <zyp> I see S7PCIEPHY has a bar0_size argument, but as far as I can see, BAR0 is hardcoded to 1MB in the .xci -- what is then the point of the argument?

11:52 <zyp> also, apart from changing the .xci, what would be required to support more than one BAR?

12:06 <_florent_> zyp: we were previously integrating the pre-generated verilog and passing the bar0 size argument to them, but i changed this to use the .xci and generate the verilog when building the project

12:06 <_florent_> bar0 size is parameter is still used for address masking on the wishbone bridge IIRC

12:08 <_florent_> i don't think supporting multiple bar0 would be too complicated, we would need to get the bar information from the incoming TLP

12:14 <TMM> acathla: sure, required but not sufficient :) Making a choice what direction to go to though!