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<somlo>
_florent_: is there an implicit "polarity" assumption when initializing an AXI2Wishbone() converter (i.e., axi==master, wishbone==slave)? I need a converter where AXI is the slave and WB is master
<zyp>
yeah, AXI2Wishbone is AXI master
<zyp>
there's a Wishbone2AXILite that I guess might work for you?
<zyp>
not very familiar with AXI, but my understanding is that lite is a subset that doesn't support bursts, so I suspect it might not be so hard to connect an AXI-lite master to an AXI slave
<somlo>
zyp: yeah, I just RTFM-ed and figured out that an AXILite master should be able to drive an AXI slave with no extra fuss
<somlo>
so I should have everything I need to get it to work (famous last words) :)
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