09:07 <acathla> Is there a reason why only one UART could work in a litex design? I crossed phy and uarts to check, and went back to first code, now the first uart is not working and the second is (which was the opposite...) There is some magic here

09:10 <_florent_> acathla: the CPU will only support one UART, but you can have several UARTs in a design

09:11 <_florent_> acathla: that's the case for example for the Crossover UART where a main UART is used by the CPU a xover UART is used by the external bridge

09:12 <acathla> Do you have an example of xover uart on an usb bridge? It's for later, but will be usefull

09:16 <_florent_> acathla: i'm not very familiar with the usb bridge, but the UARTCrossover is here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/uart.py#L381

09:16 <tpb> Title: litex/uart.py at master · enjoy-digital/litex · GitHub (at github.com)

09:16 <_florent_> that's basically two UARTs interconnected

09:18 <acathla> Ok, thank you.

14:07 <somlo> _florent_: sometime after 8143f1a0 rocket hangs at "liftoff!" -- probably some subtle corruption of the data being read from spi-sdcard?

14:09 <somlo> ignore me if you're still in the middle of working on it :)

16:42 <_florent_> somlo: i was trying to avoid the 32-bit SPI and just optimize the transfers with the 8-bit SPI, is the upstream code working for you? or is 8143f1a0 the last working commit?

17:15 <somlo> _florent_: 8143f1a0 or 754f140a is the breaking change; last known working commit (with spi-sdcard) was ac35e158

17:22 <_florent_> somlo: ok thanks