_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<futarisIRCcloud> What's the microwatt potato UART mentioned in the Renode 1.10 release notes?
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<trabucayre> _florent_: I try to adapt zybo_z7 to use litex with my redpitaya.
<trabucayre> After some (ugly) modifications the bit is produces, with bootgen I produce the bit.bin and (finally) through linux and fpga_mgr I load the bitstream.
<trabucayre> gateware is working and linux don't freeze (the bitstream is correct with ps7 ip present)
<trabucayre> Now I try to read/write using devmem but I'm unable to change something. After some read it's seems CSR base addr is 0x8200_0000 (is somewhere in GP1 address space), if I try to read/write, the system freeze (I suspect GP1 not initialized). Have you some advice to correct this (xci configuration to modify) ?
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<tpb> Title: cpu/zynq7000: set csr map to 0x00000000. · enjoy-digital/litex@3ff1bca · GitHub (at github.com)
<_florent_> it will force the csr map to 0x00000000, you should then be able to access the CSR at the base address you specified here: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/zybo_z7.py#L66
<tpb> Title: litex-boards/zybo_z7.py at master · litex-hub/litex-boards · GitHub (at github.com)
<trabucayre> _florent_: yes! It's works! Thanks!
<trabucayre> now I need to cleanup all hacks and PR!
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