_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<somlo> looks like rocket gateware grew by 4-6% since March (used to get around 100% TRELLIS_LICE utilization on the versa (sometimes even below, which then allowed nextpnr to place and route)
<somlo> now it's 104% (including litex, which is why I'm saying it grew by *more* than 4%)
<somlo> so I'm down to nexys4ddr and the trellisboard, no more versa5g for me (for now, modulo any yosys/trellis/nextpnr improvements in density that might happen in the future)
<mithro> somlo: We should figure out what caused the growth
<somlo> my prime suspect is commit 0b35bbd40a (but that's just raw instinct, not careful analysis, so I may be completely wrong)
<somlo> that forced me to choose a bus topology in the litex base config, and I picked `WithCoherentBusTopology`, which seemed appropriate
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