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<gregdavill>
I've got an interesting bug, on the OrnageCrab I'm creating an SoC with LiteDRAM. If I load the same design to my board over JTAG it only passes the DDR3 init and memtest maybe 1/2 the time.
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<tnt>
gregdavill: something missing proper reset or not waiting for pll lock or something like that ?
<gregdavill>
That's what I'm thinking. I'm looking through the clock/reset logic.
<gregdavill>
The ECP5 also has some soft logic needed to sync up phase of the sclk and eclk signals.
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<_florent_>
scanakci: hi, yes sure, please create a PR for BlackParrot, i could see how to do to also clone basejump_stl with the blackparrot pythondata
<_florent_>
gregdavill: i also have a similar issue this week when testing doing tests with the Trellisboard, but haven't been able to look at it yet
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<somlo>
_florent_: litex-hub/linux/litex-[vexriscv|rocket]-rebase branches are now updated to 5.8.0-rc2 (and ethernet & spi-sdcard still work with rocket)
<somlo>
_florent_, benh: speaking of spi-sdcard, a bare-metal copy of boot.bin from sdcard to dram takes 10 seconds, whereas dd-ing the same file from /dev/mmcblk0p1 (mounted as /mnt) to /dev/null takes 9 minutes.
<somlo>
_florent_, benh: I'm going to dig through the spi and mmc layers to see if I can spot any bottlenecks
<somlo>
_florent_, benh: but before I go down that road, is it completely unreasonable that adding all the layers (spi, mmc, the linux vfs layer, etc.) on a cpu running at 60 MHz might just add enough overhead to explain a significant portion of that discrepancy ?
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<_florent_>
somlo: thanks for updating the branches, i'll continue working on LiteSDCard next week and also want to do tests with Linux and spisdcard.
<_florent_>
the spisdcard in Linux should probably be faster, what really makes a difference is optimizing the block transfers functions: